参数资料
型号: IPT-C2H-NIOS
厂商: Altera
文件页数: 86/138页
文件大小: 0K
描述: C2H COMPILER FOR NIOS II
标准包装: 1
系列: Nios®II
类型: Nios II
功能: C 到硬件编译器
许可证: 初始许可证
Scheduling
Figure 3–23 illustrates how the C2H Compiler schedules successive
iterations of the loop shown in Figure 3–22 , based on the restrictions
imposed by hash . State 1 cannot execute until the previous iteration has
completed State 2. The C2H Compiler schedules the states as shown in
Figure 3–23 to satisfy the loop-carried dependency.
Figure 3–23. Pipelined Loop Iterations with a Loop-Carried Dependency
In Figure 3–23 , the cyclic arrow for hash in Figure 3–22 translates to
straight arrows between iterations.
Pipelining Avalon-MM Read Transfers from Multiple Iterations
As discussed in section “Read Operations with Latency” on page 3–37 ,
the C2H Compiler is aware of read latency in slave memories. Master
ports on C2H accelerators can use Avalon-MM pipelined read transfers,
which allow multiple read transfers to be pending at a given time. As a
result, for a loop that reads from memory with latency, the next iteration
of the loop can begin fetching data before data from the previous iteration
has returned. For such a loop, the C2H Compiler creates a master port
3–46
Nios II C2H Compiler User Guide
9.1
Altera Corporation
November 2009
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