参数资料
型号: ISL6232EVAL1
厂商: Intersil
文件页数: 13/25页
文件大小: 0K
描述: EVALUATION BOARD 1 ISL6232
标准包装: 1
主要目的: DC/DC,LDO 步降
输出及类型: 4,非隔离
输入电压: 5.5 ~ 25 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6232
ISL6232
VIN: 5.5V TO 22V
C13
0.1μF
5V ALWAYS ON
VIN
VCC
LDO5
C14
C6
C10
10μF
BOOT3
ISL6232
BOOT5
1μF
C1
10μF
4.7μF
Q3
Q1
OUT3
3.3V/5A
C11
220μF
12m Ω
4.0V
IRF7807V
L2:4.7μH L2: 4.7?H
Rdc218mW RDC2:12m Ω
C15: 0.47μF R9: 1.0k Ω
Q4
IRF7811AV
R4: 2.0k Ω
C9
0.1μF
UGATE3
PHASE3
LGATE3
CS3
UGATE5
PHASE5
LGATE5
PGND
C4
0.1μF
IRF7807V
L1:6.8μH RDC1:12m Ω
L1:6.8?H Rdc1:22mW
R7:1.5k Ω C8: 0.47μF
Q2
IRF7811AV
R8: 3k Ω
OUT5
5V/5A
C2
180μF
12m Ω
6.3V
CS5
OUT3
OUT5
GND
C3 R3
270pF 300k Ω
FB3
COMP3
FB5
COMP5
REF
R5 C5
390k Ω 270pF
VCC
R6
100k Ω
SKIP#
PGOOD
C7
0.22μF
REF
ON
OFF
EN3
SHDN#
EN5
LDO3
VCC
3.3V ALWAYS ON
C12
4.7μF
FIGURE 29. ISL6232 TYPICAL APPLICATION CIRCUIT WITH DCR CURRENT SENSING
Theory of Operation
The ISL6232 is a high-efficiency quad output controller
optimized for converting battery, wall adapter, or network DC
input voltage into system supply voltages required for
portable applications where high efficiency and low
quiescent supply current are required. The ISL6232
includes two PWM controllers that are fixed at 5V and 3.3V
respectively, or they can be programmed from 0.8V to 5.5V.
Figure 30 shows its functional block diagram. ISL6232 uses
a constant-frequency, 300kHz, peak current-mode PWM
control scheme with 180 o out-of-phase operation for
reducing the input ripple current and also ESR requirement
of the input capacitors. Light-load efficiency is improved by
the variable-frequency pulse-skipping operation that reduces
switching losses and gate-charge losses. In order to
eliminate the audio noise at extremely light load condition,
the ultrasonic pulse skipping mode is selectable by tying
13
SKIP# pin to REF so that a minimum 25kHz switching
frequency can be maintained.
Each switching-mode step-down circuit includes two
external N-MOSFETs and an LC output filter. The output
voltage is the average AC voltage at PHASE node, which is
regulated by changing the duty cycle of the external
N-MOSFETs. The gate-drive signal to the high side
MOSFET must exceed VIN voltage and is provided by a
0.1μF boost capacitor, which is connected between BOOT
and PHASE.
FN9116.1
April 20, 2009
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