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参数资料
| 型号： | ISL6232EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 23/25页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD 1 ISL6232 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 4，非隔离 |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6232 |
ISL6232
R2
Vo
C3
V FB
V REF
-
+
GM
V COMP
Example: V IN = 12V, V o = 5V, I o = 5A, f s = 300kHz,
C o = 180μF/12m Ω , L = 6.8μH, g m = 100μs, R T = 0.128
(R cs = 8m Ω , A c = 16), V FB = 0.8V, S e = 1.5 × 10 5 V/s,
S n = 1.318 × 10 5 V/s, f c = 45kHz, then compensator
resistance R 1 = 400k Ω .
Put the compensator zero at 1.5kHz (~1.5x C o R o) , and put
the compensator pole at esr zero which is 49kHz. The
R1
compensator capacitors are:
C1
C2
C 1 = 270pF, C 2 = 10pF (There is approximately 8pF
parasitic capacitance from V COMP to GND; Therefore, C 2
optional).
Figure shows the simulated voltage loop gain. It is shown
that it has 30kHz loop bandwidth with 85° phase margin and
FIGURE 33. TYPE II COMPENSATOR
Figure 33 shows the type II compensator and its transfer
function is expressed as Equation 29:
20dB gain margin.
60
40
? 1 + ------------- ? ? 1 + ------------- ?
ω cz1 ? ?
ω cz2 ?
v ? comp
g m
v FB C 1 + C 2 S ? 1 + ---------- ?
ω cz1 = --------------- , ω cz2 = --------------- , ω cp = -----------------------
S S
?
S ) = ----------------- = --------------------- ---------------------------------------------------------
S
? ω ?
cp
where:
1 1 C 1 + C 2
R 1 C 1 R 2 C 3 R 1 C 1 C 2
(EQ. 29)
20
0
-20
-40
-60
V LOOP
100
1·10 3
1·10 4
1·10 5
1·10 6
Loop bandwidth f c : ? -- 4 - to ------ ? f s
COMPENSATOR DESIGN GOAL
High DC gain
? 1 1 ?
10
110
FREQUENCY (Hz)
Put compensator zero ω cz1 = ( 1to3 ) R C -
1
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
--------------
o o
Put one compensator pole at zero frequency to achieve high
DC gain, and put another compensator pole at either esr
85
60
35
10
-15
V LOOP
zero frequency or half switching frequency, whichever is
lower. ω CZ2 is an internal zero due to 8pF and 600k Ω.
-40
100
1·10 3
1·10 4
1·10 5
1·10 6
The loop gain T v (S) at cross over frequency of f c has unity
gain. Therefore, the compensator resistance R 1 is
determined by Equation 30.
FIGURE 34. SIMULATED LOOP GAIN
12V Auxiliary Supply
R 1 = -----------------------------------
2 π f c V o C o R T
g m V FB
(EQ. 30)
A flyback transformer, or coupled inductor can be substituted
for the inductor in 5V or 3.3V supply to generate an 12V
where g m is the trans-conductance of the voltage error
amplifier. Compensator capacitor C 1 is then given by
Equation 31.
auxiliary output as shown in Figure 35, which can be used to
drive N-channel MOSFETs. The ISL6232 is particularly well
suited for such applications because it can be configured in
ultrasonic or forced PWM mode to ensure good load
C 1 = ----------------- , C 2 = -------------------------
1 1
R 1 ω cz 2 π R 1 f esr
23
(EQ. 31)
regulation when the main supplies are in light load
conditions. An additional post-regulation circuit can be used
to improve load regulation if necessary.
FN9116.1
April 20, 2009
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