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参数资料
| 型号： | ISL6232EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 22/25页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD 1 ISL6232 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 4，非隔离 |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6232 |
ISL6232
Loop Compensation Design
ISL6232 uses constant frequency peak current mode control
architecture to achieve fast loop transient response. An
accurate current sensing resistor in series with the output
CURRENT SAMPLING TRANSFER FUNCTION H e (S):
In current loop, the current signal is sampled every switching
cycle. The following transfer function is shown in
Equation 22:
H e ( S ) = ------- + --------------- + 1
ω n Q n
ω n
Q n = – --- , = ω n = π f s
inductor, or DCR of the output inductor, is used for peak
current control signal and overcurrent protection. The
inductor is not considered as a state variable since its peak
current is constant, and the system becomes single order
system. It is much easier to design a type II compensator to
2
S S
2
where Q n and ω n are given by
2
π
(EQ. 22)
stabilize the loop than to implement voltage mode control.
Peak current mode control has inherent input voltage
feed-forward function to achieve good line regulation.
Power Stage Transfer Functions
Transfer function F 1 (S) from control to output voltage is:
^
L
i L
i in
1 + ------------
F 1 ( S ) = ------ = V in ---------------------------------------
d ?
------- + --------------- + 1
ω o Q p
ω o
Figure 32 shows the small signal model of the synchronous
buck regulator.
^ ^
v o
2
2
S
?
v o ω esr
S S
(EQ. 23)
V in
1
1
Where ω esr = --------------- , Q p ≈ R o ------ o - , ω o = ---------------
R c C o
LC o
+
^
IL d ^
1:D
Vin d ^
RT
Rc
Ro
C
L
Transfer function F 2 (S) from control to inductor current is
given by Equation 24:
1 + ------
F 2 ( S ) = ---- = --------------------- ---------------------------------------
ω o Q p
ω o
where ω z = ---------------
d ^
Fm
+
He(S)
T i (S)
v ^ comp
-Av(S)
Co
T v(S)
K
S
I
? o V in ω z
d R o + R L S S
------- + --------------- + 1
2
1
R o C o
Current loop gain T i (S) is expressed as Equation 25:
T i ( S ) = R T F m F 2 ( S ) H e ( S )
(EQ. 24)
(EQ. 25)
FIGURE 32. SMALL SIGNAL MODEL OF SYNCHRONOUS
BUCK REGULATOR
The voltage loop gain with open current loop is shown in
Equation 26:
PWM COMPARATOR GAIN F M
T v ( S ) = KF m F 1 ( S ) A v ( S )
(EQ. 26)
The PWM comparator gain Fm for peak current mode
control is given by Equation 20:
The Voltage loop gain with current loop closed is given by
Equation 27:
( S e + S n ) T s
F m = ----------------- = --------------------------------
? v
T v ( S )
1 + T i ( S )
?
d 1
comp
(EQ. 20)
L v ( S ) = ------------------------
(EQ. 27)
V in – V o
S n = R t ---------------------
V FB
FB is the feedback voltage of the voltage
Where
1 + ------------
L v ( S ) = ----------- --------------------- ---------------------- ---------------- , ω p ≈ ---------------
Where S e is the slew rate of the slope compensation and S n
is given by Equation 21:
(EQ. 21)
L
where R T is trans-resistance, and is the product of the
current sensing resistance and gain of the current amplifier
in current loop.
22
K = ----------- , V
V o
error amplifier. If T i (S)>>1, then Equation 27 can be
simplified as shown in Equation 28:
S
V FB R o + R L ω esr A v ( S ) 1 (EQ. 28)
S
V o R T 1 + ------- H e ( S ) R o C o
ω p
From Equation 28, it is shown that the system is a single
order system, which has a single pole located at ω p before
the half switching frequency. Therefore, a simple type II
compensator can be easily used to stabilize the system.
FN9116.1
April 20, 2009
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