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参数资料
| 型号： | ISL6232EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 16/25页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD 1 ISL6232 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 4，非隔离 |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6232 |
ISL6232
slope-compensation ramp is summed into the main PWM
comparator. During the off cycle, the external high side
MOSFET turns off and the external low side MOSFET turns
on. The inductor releases the stored energy as its current
ramps down while still providing current to the output. The
output capacitor stores the charge when the inductor current
exceeds the load current and releases the charge when the
inductor current is lower, smoothing the voltage across the
load. During an overcurrent or short-circuit condition, it
immediately turns off the high side MOSFET and turns on
the low side MOSFET. This peak current limit prevents the
inductor from saturation. If the overcurrent still exists at the
rising edge of the next clock, the high side MOSFET will stay
off and the low side MOSFET remains on to let the inductor
When SKIP# = VCC, the controller always operates in forced
PWM mode for the lowest noise and zero-cross detection is
bypassed. The inductor current becomes negative at light
load condition because the PWM loop tries to maintain a
duty cycle set by V OUT /V IN , leading to poor efficiency at light
loads. During forced PWM operation, each clock rising edge
sets the main PWM latch that turns on the high side switch
for a period determined by the duty cycle. As the high side
MOSFET turns off, the synchronous rectifier latch sets and
the low side MOSFET turns on. The low side MOSFET stays
on until the beginning of the next clock cycle. Table 1 shows
the operation mode.
TABLE 1. OPERATION MODE TABLE
current ramp down.
When SKIP# = GND, the efficiency is automatically
optimized throughout the entire load current range. Skip
SKIP#
GND
MODE
Skip
LOAD
CONDITION
Light
DESCRIPTION
Pulse skipping, DCM. Turn
off UGATE when the
mode significantly improves light-load efficiency by reducing
the effective frequency, which reduces switching losses. The
inductor current reaches the
skip current threshold.
automatic transition to skip mode is determined by the
current’s zero-cross comparator, which detects inductor
current zero crossing and turns off the low side MOSFET.
The boundary is set by Equation 1:
V OUT ( 1 – D )
(EQ. 1)
2Lf
I OUT = ------------------------------------
s
GND
REF
PWM
Ultrasonic
Skip
Heavy
Light
Constant frequency PWM
Pulse skipping, DCM. Turn
on LGATE if there is no
switching after 30μs. Turn it
off once it reaches negative
current limit or PWM
comparator's output has
toggled to high before the
where D = duty cycle, f s = switching frequency, L = inductor
next clock cycle.
value, I OUT = output loading current, V OUT = output voltage.
The PWM controller keeps the peak inductor current about
15% of the overcurrent limit in an active cycle, thus allowing
REF
VCC
VCC
PWM
PWM
PWM
Heavy
Light
Heavy
Constant frequency PWM
Constant frequency PWM
Constant frequency PWM
subsequent cycles to be skipped as long as the COMP pin
V NLIM
I = ------------------- (EQ. 2)
R CS
voltage is low enough. The switching waveform at light load
behaves noisy and is asynchronous due to pulse skipping.
Skip mode transits smoothly to fixed-frequency PWM
operation as load current increases.
When SKIP# = REF, the ultrasonic mode is enabled so that
the minimum switching frequency can be maintained higher
than 25kHz. This ultrasonic pulse-skipping mode eliminates
the audio noise that can occur in skip mode at very light load
condition. Ultrasonic pulse skipping occurs if no switching
has taken place within the last 30μs. The low side MOSFET
turns on to induce a negative inductor current. Then, the
high side MOSFET turns on when the inductor current
reaches the negative current limit, or when the PWM
comparator output has toggled to high before the next clock
cycle. The negative current limit is determined by
Equation 2:
NLIM
where V NLIM is the negative current limit threshold and R CS
is current sense resistance.
16
UGATE and LGATE Drivers
A 0.1μF capacitor connected between BOOT and PHASE,
as well as the internal Schottky diode connected from LDO5
to BOOT, generate the gate drive for the high side MOSFET.
When the low side MOSFET turns on, PHASE goes to
PGND. LDO5 charges the bootstrap capacitor through the
Schottky diode. When the low side MOSFET turns off and
the high side MOSFET turns on, PHASE voltage goes to
V IN . The Schottky diode prevents the capacitor from
discharging into LDO5. The LGATE synchronous rectifier
drivers are powered by LDO5.
Both UGATE and LGATE gate drivers sink 2A peak current
out of gate terminal, ensuring adequate gate drive for high-
current applications. The internal pull-down transistors that
drive LGATE low have a 1 Ω typical ON-resistance. These
low ON-resistance pull-down transistors can prevent LGATE
from being pulled up during the fast rise time of the PHASE
nodes due to capacitive coupling from the drain to the gate
of the low side MOSFETs. In the case of high-current
applications, some combinations of both high side and low
side MOSFETs can still cause sufficient gate-drain coupling,
which leads to shoot-through currents and poor efficiency. To
FN9116.1
April 20, 2009
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