参数资料
型号: ISL6232EVAL1
厂商: Intersil
文件页数: 15/25页
文件大小: 0K
描述: EVALUATION BOARD 1 ISL6232
标准包装: 1
主要目的: DC/DC,LDO 步降
输出及类型: 4,非隔离
输入电压: 5.5 ~ 25 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6232
ISL6232
COMP
SKIP#
BOOT
0.8V
EAMP
+
COMP
UGATE
SOFT-
START
SLOPE
COMP
+
CLK
PWM/SKIP
LOGIC
CONTROLLER
LDO5
PHASE
LGATE
DC
OFFSET
FB
0.2V
+
UV
OV
+ +
CSA
? 20
x16
CS
OUT
+
OUT
OCP
+
SKIP
1.0V
0.2V
PGOOD
+
0.72V
OV
+
+ +
Zero
Cross
ZERO
CROSS
0.06V
0.9V
0.1V
UV
20ms
BLANKING
0.6V
NOCP
NCSA
x8
FIGURE 31. SYNCHRONOUS BUCK PWM CONTROLLER BLOCK DIAGRAM
drivers. The low side drivers are directly powered from LDO5
and the high side drivers are indirectly powered from LDO5
through the internal Schottky diode and external bootstrap
capacitor. Only after soft-start is finished and when OUT5 is
above 4.75V, an automatic switch-over circuit turns off the
internal LDO5 regulator and powers the device from OUT5.
This prevents the LDO5 and LDO3 from a voltage dip during
the switch-over. It switches back to LDO5 when OUT5 is
disabled for EN5 = 0. Similary, only after soft-start is finished
and when OUT3 is above 3.0V, it turns off the 3.3V LDO3
regulator and powers the device from OUT3. It switches
back to LDO3 just before OUT3 is disabled.
ISL6232 has internal soft-start to control the inrush current.
This soft-stop feature avoids negative output voltage for
undervoltage protection and overcurrent protection so that
the part can be shut down by first discharging OUT3 or
OUT5 through an internal 20 Ω switch and damping the
15
inductor current. Finally, thermal shutdown is included in
ISL6232 to protect the part from overheating.
PWM Controller
The two-buck controllers are nearly identical. The only
difference is the fixed output voltage, 3.3V vs 5V. Both buck
controllers use a peak current-mode PWM control scheme.
For peak current mode control, the system can be unstable
when the duty cycle is higher than 0.5. A slope
compensation signal is used to stabilize the system. A PWM
comparator compares the integrated voltage feedback signal
(COMP) with the sum of the amplified current-sense signal
and the slope-compensation ramp. At each rising edge of
the internal clock, the high side MOSFET turns on until the
PWM comparator trips. During this on-time, current ramps
up through the inductor, sourcing current to the output and
storing energy in the inductor. The current-mode feedback
system regulates the peak inductor current as a function of
the output voltage error signal. To preserve loop stability, a
FN9116.1
April 20, 2009
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