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参数资料
| 型号： | ISL6232EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 17/25页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD 1 ISL6232 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 4，非隔离 |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6232 |
ISL6232
get around this situation, a small resistor (a few ohms) in
series with the BOOT pin can be added to increase the
current mode (CCM) and discontinuous current mode
(DCM). In CCM mode, the boundary is set by Equation 3,
I OUT = -----------------------------------
turn-on time of the high side MOSFETs at the cost of
efficiency.
Dead-time control circuitry is also implemented to monitor
V OUT ( 1 – D )
2Lf s
(EQ. 3)
the UGATE and LGATE voltages so that one of the external
MOSFETs can be prevented from turning on before the other
one completely turns off. This method can allow operation
without shoot-through with a wide selection range of external
MOSFETs, minimizing delays and maintaining efficiency. To
achieve this, the trace from UGATE and LGATE to the
where D = duty cycle, f s = switching frequency, L = inductor
value, IOUT = output loading current, VOUT = output
voltage.
However, the boundary is set by the following formula,
Equation 4, in DCM condition.
I OUT = -----------------
MOSFET gates must be low resistance and low inductance.
Otherwise, the control circuitry will regard the MOSFET gate
V SKIP
2R CS
(EQ. 4)
as in the off-state when there is still some charge left on the
gate.
CURRENT SENSE INPUTS, CS AND OUT
An internal current-sense amplifier produces a current signal
proportional to the voltage generated by the sense
resistance and the inductor current (R CS *I L ). The amplified
current-sense signal and the internal slope-compensation
signal sum together at the comparator inverting input. The
PWM comparator turns off the high side MOSFET when this
summed voltage exceeds the COMP voltage of the error
amplifier.
The ISL6232 has a positive current limit threshold of 80mV
with a ±20% tolerance. Whenever the voltage difference
between CS and OUT exceeds 80mV, the high side
MOSFET turns off and the low side MOSFET turns on. This
lowers the duty cycle and causes the output voltage to drop
until the current limit is no longer exceeded.
The external low-value sense resistor, R CS , should be
picked for 65mV/I PEAK , where I PEAK is the required peak
inductor current to support the full load current. Also, the
other components must be chosen to sustain continuous
current of 95mV/R CS . It is useful to wire the current-sense
inputs with a twisted pair, which can reduce the possible
noise picked up at CS and OUT as well as avoid unstable
switching.
A negative current limit threshold, typical of 20mV, is
implemented to prevent excessive reverse inductor currents
when OUT dumps charges. This negative current limit is
used to determine when the low side MOSFET should turn
off at ultrasonic pulse skipping mode.
Mode Transition Between DCM and CCM
The automatic transition to skip mode is determined by the
current zero-cross comparator, which detects the inductor
current's zero crossing and turns off the low side MOSFET.
The threshold between pulse skipping pulse frequency
modulation (PFM) and non-skipping PWM can not
completely coincide with the boundary between continuous
17
where VSKIP is the current limit threshold at skip mode. The
above two boundary values can not be completely matched
due to the tolerance of the pulse skipping current limit
threshold, inductance, frequency, and line input voltage. The
ISL6232 is designed in such a way that it operates in a
mixed mode between DCM mode CCM mode during the
mode transition, which may have one longer pulse and is
followed by one shorter pulse. But this does not affect the
output ripple voltage. This is a normal operation and it is not
the loop stability issue. The inductor current is regulated in
the CCM mode to meet the load current requirement since
the inductor current is fixed in the DCM mode during the
mixed mode operation.
POWER GOOD (PGOOD)
PGOOD is kept low during soft-start. When both OUT3 and
OUT5 voltages reach 90% of the regulation points, PGOOD
toggles to high after the end of soft-start period. When either
output turns off or is 10% below its regulation point, or a fault
occurs in either output, PGOOD goes low. PGOOD is set to
low during shutdown, standby, and soft-start.
DISCHARGE MODE
When the output is disabled by toggling EN3 or EN5 from
high to low or latched off due to the undervoltage or
overcurrent fault, it is discharged through an internal 20 Ω
switch from PHASE to PGND until the output drops to 0.3V.
After the output drops below 0.3V, LGATE is forced to high to
discharge the output to ground. LDO5, VCC, and REF are
active at this mode.
POWER-ON RESET, DIGITAL SOFT-START, AND UVLO
When V IN rises above approximately 3.8V, power-on reset
occurs. After internal reference voltages and bias currents
are ready, both LDO3 and LDO5 are enabled. After LDO5
reaches undervoltage lockout (UVLO) voltage, 4.3V, the
buck controller is enabled if either EN3 or EN5 is tied to
VCC. Then, the internal digital soft-start circuitry begins to
charge-up the output capacitor of the buck controller
gradually in 44 steps within 1.2ms (typ), so that the V IN
in-rush current can be reduced. Each buck controller
FN9116.1
April 20, 2009
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