参数资料
| 型号： | ISL6277IRZ |
| 厂商： | Intersil |
| 文件页数： | 16/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6277
1
2
3
4
5
6
7
8
VDD
SVC
SVD
VOTF
SVT
ENABLE
PWROK
Telemetry
Telemetry
V CORE / V CORE_NB
METAL_VID
V_SVI
PGOOD & PGOOD_NB
Interval 1 to 2: ISL6277 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL6277 is prepared for SVI commands.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6277 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes.
Post 8: Telemetry is clocked out of the ISL6277.
FIGURE 12. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
Start-up Timing
With VDD above the POR threshold, the controller start-up
sequence begins when ENABLE exceeds the logic high threshold.
Figure 13 shows the typical soft-start timing of the Core and
Northbridge VRs. Once the controller registers ENABLE as a high,
the controller checks that state of a few programming pins
during the typical 8ms delay prior to beginning soft-starting the
Core and Northbridge outputs. The pre-PWROK Metal VID is read
from the state of the SVC and SVD pins and programs the DAC,
the programming resistors on COMP, COMP_NB, and FCCM_NB
are read to configure internal drivers, switching frequency, slew
rate, output offsets. These programming resistors are discussed
VDD
ENABLE
DAC
PGOOD
PWROK
VIN
8ms
SLEW RATE
MetalVID VID COMMAND
VOLTAGE
in subsequent sections. The ISL6277 use a digital soft-start to
ramp up the DAC to the Metal VID level programmed. The
soft-start slew rate is programmed by the FCCM_NB resistor
which is used to set the VID-on-the-Fly slew rate as well. See the
VID-on-the-Fly Slew Rate Selection section for more details on
selecting the FCCM_NB resistor. PGOOD is asserted high at the
end of the soft-start ramp.
16
FIGURE 13. TYPICAL SOFT-START WAVEFORMS
Voltage Regulation and Load Line
Implementation
After the soft-start sequence, the ISL6277 regulates the output
voltages to the pre-PWROK metal VID programmed, see Table 6.
The ISL6277 controls the no-load output voltage to an accuracy of
±0.5% over the range of 0.75V to 1.55V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
FN8270.1
March 8, 2012
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| ISL6277IRZ-T | 功能描述:IC PWM REG MULTIPH AMD 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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