参数资料
| 型号： | ISL6277IRZ |
| 厂商： | Intersil |
| 文件页数： | 18/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6277
The ISL6277 will adjust the phase pulse-width relative to the
Rewriting Equation 11 gives Equation 13:
other phases to make V ISEN1 = V ISEN2 = V ISEN3 , thus to achieve
I L1 = I L2 = I L3 , when R dcr1 = R dcr2 = R dcr3 and
R pcb1 = R pcb2 = R pcb3 .
Using the same components for L1, L2 and L3 provides a good
match of R dcr1 , R dcr2 and R dcr3 . Board layout determines R pcb1 ,
R pcb2 and R pcb3 . It is recommended to have a symmetrical
layout for the power delivery path between each inductor and the
output voltage rail, such that R pcb1 = R pcb2 = R pcb3 .
V 1p – V 1n = V 2p – V 2n
Rewriting Equation 12 gives Equation 14:
V 2p – V 2n = V 3p – V 3n
Combining Equations 13 and 14 gives:
V 1p – V 1n = V 2p – V 2n = V 3p – V 3n
(EQ. 13)
(EQ. 14)
(EQ. 15)
ISEN3
C isen
PHASE3
R isen
R isen
V3p
L3
I L3
R dcr3
V 3n
R pcb3
Therefore:
R dcr1 ? I L1 = R dcr2 ? I L2 = R dcr3 ? I L3
(EQ. 16)
PHASE2
INTERNAL
TO IC
ISEN2
C isen
ISEN1
C isen
R isen
V2p
R isen
R isen
R isen
PHASE1 V1p
R isen
R isen
L2
L1
I L2
I L1
R dcr2
V 2n
R dcr1
V 1n
R pcb2
R pcb1
V o
Current balancing (I L1 = I L2 = I L3 ) is achieved when
R dcr1 = R dcr2 = R dcr3 . R pcb1 , R pcb2 and R pcb3 do not have any
effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, the R 3 ? modulator can naturally achieve excellent
current balancing during steady state and dynamic operations.
Figure 17 shows the current balancing performance of the
evaluation board with load transient of 12A/51A at different rep
rates. The inductor currents follow the load current dynamic
change with the output capacitors supplying the difference. The
R isen
FIGURE 16. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
inductor currents can track the load current well at a low
repetition rate, but cannot keep up when the repetition rate gets
into the hundred-kHz range, where it is out of the control loop
bandwidth. The controller achieves excellent current balancing in
all cases installed.
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 15, asymmetric layout causes
different R pcb1 , R pcb2 and R pcb3 values, thus creating a current
imbalance. Figure 16 shows a differential sensing current
balancing circuit recommended for ISL6277. The current sensing
traces should be routed to the inductor pads so they only pick up
the inductor DCR voltage. Each ISEN pin sees the average voltage
of three sources: its own, phase inductor phase-node pad, and
the other two phase inductor output side pads. Equations 8
through 10 give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n + V 3n
V ISEN2 = V 1n + V 2p + V 3n
V ISEN3 = V 1n + V 2n + V 3p
(EQ. 8)
(EQ. 9)
(EQ. 10)
The ISL6277 will make V ISEN1 = V ISEN2 = V ISEN3 as shown in
Equations 11 and 12:
V 1p + V 2n + V 3n = V 1n + V 2p + V 3n
V 1n + V 2p + V 3n = V 1n + V 2n + V 3p
18
(EQ. 11)
(EQ. 12)
FN8270.1
March 8, 2012
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