参数资料
| 型号： | ISL6277IRZ |
| 厂商： | Intersil |
| 文件页数： | 26/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6277
Dynamic Load Line Slope Trim
The ISL6277 supports the SVI2 ability for the processor to
manipulate the load line slope of the Core and Northbridge VRs
independently using the serial VID interface. The slope
manipulation applies to the initial load line slope. A load line
slope trim will typically coincide with a VOTF change. See
Table 11 for more information about the load line slope trim
feature of the ISL6277.
TABLE 11. LOAD LINE SLOPE TRIM DEFINITION
The ISL6277 also features a way-overcurrent [WOC] feature which
immediately takes the controller into shutdown. This protection is
also referred to as fast overcurrent protection for short-circuit
protection. If the IMON current reaches 15μA, WOC is triggered.
Active channels are tri-stated and the controller is placed in
shutdown and PGOOD is pulled low. There is no fault timer on the
WOC fault, the controller takes immediate action. The other
controller output is also shutdown within 10μs.
Designing the current feedback components and setting the OCP
level require knowing the IDDSpike value (EDC) outlined for the
LOAD LINE SLOPE TRIM [2:0]
000
001
010
011
100
101
110
111
DESCRIPTION
Disable LL
-40% m ? Change
-20% m ? Change
No Change
+20% m ? Change
+40% m ? Change
+60% m ? Change
+80% m ? Change
AMD CPU under consideration. AMD specifications will outline a
TDC current level and an EDC current level for each CPU. The EDC
current is the maximum current the CPU can demand for a short,
thermally insignificant time. When selecting the components for
the current feedback design or using an Intersil design
spreadsheet, the EDC current is used as the full load current. The
reasoning is that the AMD CPU will view reaching the EDC current
as 100% loading. The desired droop current at full load must be
set to 45 μ A. The controller generates a current across the IMON
resistor that is ? of the average value of the ISUM current. The
droop current is 5/4 greater than the ISUM current, so for a droop
current of 45 μ A the ISUM current is 36 μ A. The recommended
Dynamic Offset Trim
The ISL6277 supports the SVI2 ability for the processor to
manipulate the output voltage offset of the Core and Northbridge
VRs. This offset is in addition to any output voltage offset set via
the COMP resistor reader. The dynamic offset trim can disable
the COMP resistor programmed offset of either output when
Disable All Offset’ is selected.
TABLE 12. OFFSET TRIM DEFINITION
IMON resistor value is 133k ? , 1% tolerance. At full load current,
EDC level, the resulting IMON voltage will be 1.2V and telemetry
will report 100%. If the load current continues to increase, then
the IMON voltage will continue to rise, but the telemetry will still
report 100% loading. Once the ISUM current reaches 45 μ A, the
corresponding current out of the IMON pin is 11.25 μ A and the
voltage on the IMON resistor will be 1.5V and the controller will
report an OC trip. The load current at this point is 25% higher
than the EDC current used for setting full load droop current. This
additional margin allows the AMD CPU to enter and exit the
OFFSET TRIM [1:0]
00
01
10
11
DESCRIPTION
Disable All Offset
-25mV Change
0mV Change
+25mV Change
IDDSpike performance mode without issue unless the load
current is out of line with the IDDSpike expectation.
Current-Balance
The controller monitors the ISENx pin voltages to determine
current-balance protection. If the ISENx pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
Protection Features
Core VR and Northbridge VR both provide overcurrent,
current-balance, undervoltage, and overvoltage fault protections.
The controller also provides over-temperature protection. The
following discussion is based on Core VR and also applies to the
Northbridge VR.
Overcurrent
Overcurrent protection is triggered when the voltage across the
IMON resistor is 1.5V. Within 2μs of detecting the IMON voltage,
the controller asserts VR_HOT_L low to communicate to the AMD
CPU to throttle back. A fault timer begins counting while IMON is at
or above the 1.5V threshold. The fault timer lasts 7.5μs to 11μs
and then flags an OCP fault. The controller then tri-states the
active channels and goes into shutdown. PGOOD is taken low and
a fault flag from this VR is sent to the other VR and it is shutdown
within 10μs. If the IMON voltage drops below the 1.5V threshold
prior to the fault timer count finishing, the fault timer is cleared
and VR_HOT_L is taken high.
26
latch off.
Undervoltage
If the VSEN voltage falls below the output voltage VID value plus
any programmed offsets by -325mV, the controller declares an
undervoltage fault. The controller de-asserts PGOOD and
tri-states the power MOSFETs.
Overvoltage
If the VSEN voltage exceeds the output voltage VID value plus any
programmed offsets by +325mV, the controller declares an
overvoltage fault. The controller de-asserts PGOOD and turns on the
low-side power MOSFETs. The low-side power MOSFETs remain on
until the output voltage is pulled down below the VID set value. Once
the output voltage is below this level, the lower gate is tri-stated. If
the output voltage rises above the overvoltage threshold again, the
protection process is repeated. when all power MOSFETs are turned
off. This behavior provides the maximum amount of protection
against shorted high-side power MOSFETs while preventing output
ringing below ground.
FN8270.1
March 8, 2012
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