参数资料
型号: ISL6312IRZ
厂商: Intersil
文件页数: 12/35页
文件大小: 0K
描述: IC CTRLR PWM 4PHASE BUCK 48-QFN
标准包装: 43
应用: 控制器,Intel VR10、VR11、AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.38 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6312
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry equal amounts of current at any load level. To achieve
this, the currents through each channel must be sampled
every switching cycle. The sampled currents, I n , from each
active channel are summed together and divided by the
number of active channels. The resulting cycle average
current, I AVG , provides a measure of the total load-current
demand on the converter during each switching cycle.
Channel-current balance is achieved by comparing the
sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current-
balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. In the figure, the cycle
Continuous Current Sampling
In order to realize proper current-balance, the currents in
each channel are sensed continuously every switching
cycle. During this time the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, I L . This sensed current, I SEN , is simply a
scaled version of the inductor current.
The ISL6312 supports inductor DCR current sensing to
continuously sense each channel’s current for channel-
current balance. The internal circuitry, shown in Figure 5
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending on how many channels are
operating.
average current, I AVG , is compared with the Channel 1
sample, I 1 , to create an error signal I ER .
UGATE(n)
V IN
IL
DCR
V COMP
+
-
MODULATOR
RAMP
+
-
PWM1
TO GATE
CONTROL
LOGIC
MOSFET
DRIVER
LGATE(n)
L
INDUCTOR
V L (s)
V OUT
C OUT
FILTER
f(s)
WAVEFORM
V C (s)
I ER
+
-
I AVG
÷ N
Σ
I 4
I 3
I 2
ISL6312 INTERNAL CIRCUIT
R 1
C 1
R 2*
I 1
NOTE: Channel 3 and 4 are optional.
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-
I n
SAMPLE
BALANCE ADJUSTMENT
+
-
V C (s)
ISEN-(n)
The filtered error signal modifies the pulse width
commanded by V COMP to correct any unbalance and force
I ER toward zero. The same method for error signal
correction is applied to each active channel.
I SEN
R ISEN
ISEN+(n)
*R 2 is OPTIONAL
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
Inductor windings have a characteristic distributed
PWM
SWITCHING PERIOD
I L
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel current
I L , flowing through the inductor, passes through the DCR.
Equation 3 shows the s-domain equivalent voltage, V L ,
across the inductor.
V L ( s ) = I L ? ( s ? L + DCR )
(EQ. 3)
I SEN
A simple R-C network across the inductor (R 1 and C)
extracts the DCR voltage, as shown in Figure 5. The voltage
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
12
across the sense capacitor, V C , can be shown to be
proportional to the channel current I L , shown in Equation 4.
FN9289.6
February 1, 2011
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