参数资料
| 型号： | ISL6312IRZ |
| 厂商： | Intersil |
| 文件页数： | 13/35页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ISL6312
? ------------- + 1 ?
-------------------------------------- ? DCR ? I L
V C ( s ) =
s ? L
? DCR ?
( s ? R 1 ? C + 1 )
(EQ. 4)
TABLE 1. ISL6312 DAC SELECT TABLE
DAC VERSION VRSEL PIN VID7 PIN
In some cases it may be necessary to use a resistor divider
R-C network to sense the current through the inductor. This
can be accomplished by placing a second resistor, R 2 ,
across the sense capacitor. In these cases the voltage
VR10(Extended)
VR11
AMD 5-Bit
VRSEL = GND
VRSEL = VCC/2
VRSEL = VCC
-
-
LOW
? ------------- + 1 ?
s ? L
( R 1 ? R 2 )
V C ( s ) = -------------------------------------------------------- ? K ? DCR ? I L
R 1 + R 2
across the sense capacitor, V C , becomes proportional to the
channel current I L , and the resistor divider ratio, K.
(EQ. 5)
? DCR ?
? ?
? s ? ------------------------ ? C + 1 ?
? ?
AMD 6-Bit VRSEL = VCC HIGH
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES
VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC
0 1 0 1 0 1 1 1.60000
0
1
0
1
0
1
0
1.59375
R 2
R 2 + R 1
K = ---------------------
(EQ. 6)
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1.58750
1.58125
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time
constant, then V C is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1 .
The capacitor voltage V C , is then replicated across the
sense resistor R ISEN . The current through R ISEN is
proportional to the inductor current. Equation 7 shows that
the proportion between the channel current and the sensed
current (I SEN ) is driven by the value of the sense resistor,
the resistor divider ratio, and the DCR of the inductor.
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
I SEN = K ? I L ? ------------------
DCR
R ISEN
(EQ. 7)
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1.51875
1.51250
Output Voltage Setting
The ISL6312 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel
modes of operation, each VID pin is pulled up to an internal
1.2V voltage by a weak current source (40μA), which
decreases to 0A as the voltage at the VID pin varies from 0
to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a weak 20μA
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
The ISL6312 accommodates four different DAC ranges: Intel
VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and AMD
6-bit. The state of the VRSEL and VID7 pins decide which
DAC version is active. Refer to Table 1 for a description of
how to select the desired DAC version. For VR11 setting, tie
the VRSEL pin to the midpoint of a 10k Ω (or other suitable
value) resistor divider connected from VCC to GND.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
13
FN9289.6
February 1, 2011
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