参数资料
| 型号： | ISL6313IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 36-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
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ISL6313
from shutdown mode to begin the soft-start startup
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
output voltage reaches the VID voltage plus/minus any offset
or droop voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 19.
the ISL6313 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6313 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6313 in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
t SS = t d1 + t d2 + t d3 + t d4
V OUT , 500mV/DIV
(EQ. 19)
3. The driver bias voltage applied at the PVCC pin must
t d1
t d2
t d3
t d4
t d5
reach the internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the ISL6313 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 6).
For Intel VR11 and AMD 6-bit modes of operation these are
the only conditions that must be met for the controller to
immediately begin the soft-start sequence. If running in AMD
5-bit mode of operation there is one more condition that
must be met:
4. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
EN
PGOOD
500μs/DIV
FIGURE 13. SOFT-START WAVEFORMS
During t d2 and t d4 , ISL6313 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R SS on the SS pin. The second
soft-start ramp time t d2 and t d4 can be calculated based on
Equations 20 and 21:
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
t d2 = 1.1 ? R SS ? 8 ? 10
– 3
( μ s )
(EQ. 20)
to the user designated level.
Intel Soft-Start
t d4 = V VID – 1.1 ? R SS ? 8 ? 10
– 3
( μ s )
(EQ. 21)
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
For the Intel VR11 mode of operation, the soft-start
sequence if composed of four periods, as shown in
Figure 13. Once the ISL6313 is released from shutdown and
page 20), the controller will have a fixed delay period TD1 of
typically 1.10ms. After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V
VBOOT voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed delay period t d3 , of typically
93μs. At the end of t d3 period, ISL6313 will read the VID
signals. It is recommended that the VID codes be set no
later then 50μs into period t d3 . If the VID code is valid,
ISL6313 will initiate the second soft-start ramp until the
21
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t d2 will be 880μs and the
second soft-start ramp time t d4 will be 320μs.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t d5 . The typical value
for t d5 is 93μs.
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of two periods, as shown in
Figure 14. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t dA of typically 1.10ms. After this delay period
the ISL6313 will begin ramping the output voltage to the
desired DAC level at a fixed rate of 6.25mV per step. The
time for each step is determined by the frequency of the
soft-start oscillator which is defined by the resistor R SS on
the SS pin. The amount of time required to ramp the output
FN6448.2
September 2, 2008
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| ISL6314CRZ | 功能描述:电压模式 PWM 控制器 1-PH PWM CNTRLR W/1 INTEGRTD DRVRS 32LD RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6314CRZ-T | 功能描述:IC CTRLR PWM 1PHASE BUCK 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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| ISL6314IRZ | 功能描述:IC CTRLR PWM 1PHASE BUCK 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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