参数资料
型号: ISL6313IRZ-T
厂商: Intersil
文件页数: 22/33页
文件大小: 0K
描述: IC CTRLR PWM 2PHASE BUCK 36-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 4,000
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 带卷 (TR)
ISL6313
voltage to the final DAC voltage is referred to as t dB , and can
be calculated as shown in Equation 22:
the output drives are enabled at the end of the soft-start
period, leading to an abrupt correction in the output voltage
tDB = V VID ? R
SS
? 8 ? 10
– 3
( μ s )
(EQ. 22)
down to the DAC-set level.
Fault Monitoring and Protection
At the end of soft-start, PGOOD will immediately go high if
the VSEN voltage is within the undervoltage and overvoltage
limits.
V OUT , 500mV/DIV
The ISL6313 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 16
outlines the interaction between the fault monitors and the
power good signal.
t dA
t dB
I AVG
100μA
+
OCP
-
+
OCL
-
I 1
140μA
EN
VDAC + RGND
REPEAT FOR
EACH CHANNEL
PGOOD
SS
+175mV
OR
+225mV
+
OCP
-
IOUT
V OCP
500μs/DIV
FIGURE 14. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6313 also has the ability to start up into a pre-charged
1.260V
SOFT-START, FAULT
AND CONTROL LOGIC
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
VSEN
-
+
-
OVP
PGOOD
OUTPUT PRECHARGED
ABOVE DAC LEVEL
-350mV
+
UV
VDAC + RGND
ISL6313 INTERNAL CIRCUITRY
OUTPUT PRECHARGED
BELOW DAC LEVEL
FIGURE 16. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
GND>
GND>
t1 t2
t3
V OUT (0.5V/DIV)
EN (5V/DIV)
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6313 is regulating the
output voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied through a resistor to
a voltage source that’s equal to or less then VCC.
For Intel mode of operation, PGOOD indicates whether VSEN
is within specified overvoltage and undervoltage limits after a
FIGURE 15. SOFT-START WAVEFORMS FOR ISL6313-BASED
MULTI-PHASE CONVERTER
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged
level to the final level dictated by the DAC setting. Should the
output be pre-charged to a level exceeding the DAC setting,
22
fixed delay from the end of soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
EN, POR, or one of the no-CPU VID codes. In the event of
an overvoltage or overcurrent condition, or a no-CPU VID
code, the controller latches off and PGOOD will not return
high until EN is toggled and a successful soft-start is
FN6448.2
September 2, 2008
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