参数资料
型号: ISL6313IRZ-T
厂商: Intersil
文件页数: 27/33页
文件大小: 0K
描述: IC CTRLR PWM 2PHASE BUCK 36-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 4,000
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 带卷 (TR)
ISL6313
I FL
desired overcurrent trip level, I OCP , be chosen so that it’s
30% larger then the maximum load current expected.
.
V DROOP
R LL = -------------------------
(EQ. 37)
R SET = ---------------------------- ? -------------- ? ----------
100 × 10
DCR I OCP 400
– 6 N 3
*Note: R SET must be between 20k Ω and 80k Ω
(EQ. 35)
Based on the desired loadline, the loadline regulation
resistor, R FB , can be calculated from Equation 38.
R LL ? N ? R SET 3
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R 1 to match the time constants
correctly. The effects of time constant mismatch can be seen
DCR ----------
R FB = --------------------------------------- ? 400
*Note: R FB must be not exceed 4.0k Ω
(EQ. 38)
R 1 ( NEW ) = R 1 ( OLD ) ? ----------
Δ V
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 21. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
2. Record Δ V1 and Δ V2 as shown in Figure 21.
3. Select new values, R 1(NEW) , for the time constant
resistor based on the original value, R 1(OLD) , using
Equation 36.
Δ V 1 (EQ. 36)
2
In Equation 38, R LL is the loadline resistance; N is the
number of active channels; DCR is the DCR of the individual
output inductors; and R SET is the RSET pin resistor.
If no loadline regulation is required, the resistor on the FS
pin, R T , should be connected to the VCC pin. To choose the
value for R FB in this situation, please refer to “Compensation
without load-line regulation” on page 28.
IOUT Pin Resistor
A copy of the average sense current flows out of the IOUT
pin, and a resistor, R IOUT , placed from this pin to ground can
be used to set the overcurrent protection trip level. Based on
the desired overcurrent trip threshold, I OCP , the IOUT pin
R SET ? N 6
DCR ? I OCP 400
4. Replace R 1 with the new value and check to see that the
error is corrected. Repeat the procedure if necessary.
resistor, R IOUT , can be calculated from Equation 39.
R IOUT = -------------------------------- ? ----------
APA Pin Component Selection
(EQ. 39)
Δ V 1
Δ V 2
V OUT
A 100μA current flows into the APA pin and across R APA to
set the APA trip level. A 1000pF capacitor, C APA , should
also be placed across the R APA resistor to help with noise
immunity. Use Equation 40 to set R APA to get the desired
APA trip level. An APA trip level of 500mV is recommended
for most applications.
R APA = --------------------------------- = ----------------------------- = 5k Ω
Δ I
I TRAN
V APA ( TRIP ) 500mV
100 × 10 – 6 100 × 10 – 6
(EQ. 40)
Compensation
The two opposing goals of compensating the voltage
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
If loadline regulation is desired, the resistor on the FS pin,
R T , should be connected to Ground in order for the internal
average sense current to flow out across the loadline
regulation resistor, labeled R FB in Figure 7. This resistor ’s
value sets the desired loadline required for the application.
The desired loadline, R LL , can be calculated by Equation 37
where V DROOP is the desired droop voltage at the full load
current I FL.
27
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATION WITH LOAD-LINE REGULATION
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R C and C C .
FN6448.2
September 2, 2008
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