参数资料
| 型号： | ISL6328ACRZ |
| 厂商： | Intersil |
| 文件页数： | 24/33页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE REGULATOR |
| 标准包装： | 50 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
ISL6328A
commutation is t 1 and the approximated associated power loss
is P UP,1 .
1.6
? I M I PP ? ? ?
P UP , 1 ≈ V IN ? ? ------ + -------- ? ? ? ---- 1 - ? ? f S
? N 2 ? ? 2 ?
t
(EQ. 25)
1.4
1.2
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 26, the approximate
power loss is P UP,2 .
1.0
0.8
P UP , 2 ≈ V IN ? ? ------ – -------- ?
? ? ? ? f S
? t 2 ?
? 2 ?
? I M I PP ?
? N 2 ?
-----
(EQ. 26)
0.6
Q GATE = 100nC
A third component involves the lower MOSFET reverse-recovery
charge, Q rr . Since the inductor current has fully commutated to
the upper MOSFET before the lower-MOSFET body diode can
0.4
0.2
20nC
50nC
P UP , 3 = V IN ? Q rr ? f S
recover all of Q rr , it is conducted through the upper MOSFET
across VIN. The power dissipated as a result is P UP,3 .
(EQ. 27)
Finally, the resistive part of the upper MOSFET is given in
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Δ V BOOT_CAP (V)
FIGURE 15. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
I PP2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? ? ------ ? ? d + ----------
Equation 28 as P UP,4 .
2
? N ? 12
(EQ. 28)
Gate Drive Voltage Versatility
The ISL6328A provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. The controller ties the
upper and lower drive rails together. Simply applying a voltage
The total power dissipated by the upper MOSFET at full load can
now be approximated as the summation of the results from
Equations 25, 26, 27 and 28. Since the power equations depend
on MOSFET parameters, choosing the correct MOSFETs can be an
iterative process involving repetitive solutions to the loss
equations for different MOSFETs and different switching
frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor from
overcharging due to the large negative swing at the PHASE node.
This reduces voltage stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 4V and its capacitance value can be chosen from
Equation 29:
from 5V up to 12V on PVCC sets both gate drive rail voltages
simultaneously.
Package Power Dissipation
When choosing MOSFETs it is important to consider the amount
of power being dissipated in the integrated drivers located in the
controller. Since there are a total of three drivers in the controller
package, the total power dissipated by all three drivers must be
less than the maximum allowable power dissipation for the QFN
package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 29 for
thermal transfer improvement suggestions.
C BOOT_CAP ≥ ---------------------------------
Q GATE = ? ------------------------------ ? N Q1 ?
Q GATE
Δ V BOOT_CAP
? Q G1 ? PVCC ?
? V GS1 ?
(EQ. 29)
When designing the ISL6328A into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to the
gate charge of MOSFETs and the integrated driver’s internal
circuitry and their corresponding average driver current can be
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
where Q G1 is the amount of gate charge per upper MOSFET at
V GS1 gate-source voltage and N Q1 is the number of control
MOSFETs. The Δ V BOOT_CAP term is defined as the allowable
droop in the rail of the upper gate drive.
estimated with Equations 30 and 31, respectively.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 30)
I DR = ? --- ? Q G1 ? N
24
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
(EQ. 31)
FN7986.0
April 6, 2012
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