参数资料
型号: ISL6328ACRZ
厂商: Intersil
文件页数: 25/33页
文件大小: 0K
描述: IC VOLTAGE REGULATOR
标准包装: 50
系列: *
ISL6328A
V IN
L
C OUT
In Equations 30 and 31, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power loss;
the gate charge (Q G1 and Q G2 ) is defined at the particular gate to
source drive voltage PVCC in the corresponding MOSFET data
sheet; I Q is the driver total quiescent current with no load at both
drive outputs; N Q1 and N Q2 are the number of upper and lower
MOSFETs per phase, respectively; N PHASE is the number of active
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC BOOT
Inductor DCR Current Sensing Component
Fine Tuning
I
n
UGATE(n)
L
MOSFET DCR V OUT
DRIVER LGATE(n) INDUCTOR
V L (s)
V C (s)
D
R 1
C
R HI1
UGATE
G
C GD
C DS
ISL6328A INTERNAL CIRCUIT
ISENn-
R 2
R LO1
R G1
R GI1
C GS
S
Q1
I n
+
-
ISENn+
V C (s)
R ISEN
PHASE
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
I SEN
FIGURE 18. DCR SENSING CONFIGURATION
Due to errors in the inductance and/or DCR it may be necessary
PVCC
D
to adjust the value of R 1 and R 2 to match the time constants
correctly. The effects of time constant mismatch can be seen in
the form of droop overshoot or undershoot during the initial load
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C GS
S
C DS
Q2
transient spike, as shown in Figure 19. Follow the steps below to
ensure the R-C and inductor L/DCR time constants are matched
accurately.
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and Ground for
the duration of this procedure.
2. Capture a transient event with the oscilloscope set to about
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the resistive
components along the transition path and in the bootstrap diode. The
portion of the total power dissipated in the controller itself is the power
L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
3. Record Δ V1 and Δ V2 as shown in Figure 19.
dissipated in the upper drive path resistance (P DR_UP ), the lower drive
path resistance (P DR_UP ), and in the boot strap diode (P BOOT ). The rest
of the power will be dissipated by the external gate resistors (R G1 and
R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of the MOSFETs.
Figures 16 and 17 show the typical upper and lower gate drives turn-on
transition path. The total power dissipation in the controller itself, P DR ,
can be roughly estimated as:
Δ V 1
Δ V 2
V OUT
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
P DR_UP = ? ----------------------------------- + ------------------------------------- ? ? -------------------
R HI1 + R EXT1 R LO1 + R EXT1 ?
?
P DR_LOW = ? ----------------------------------- + ------------------------------------- ? ? -------------------
R HI2 + R EXT2 R LO2 + R EXT2 ?
?
N Q2
N Q1
3
P Qg_Q1
P BOOT = -------------------
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
R GI1 R GI2
3
2
R EXT1 = R G1 + ------------ R EXT2 = R G2 + ------------
25
(EQ. 32)
I TRAN
Δ I
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
FN7986.0
April 6, 2012
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