参数资料
| 型号： | ISL6545IBZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6545IBZ-TDKR |
ISL6545, ISL6545A
V OSC ? R1 ? F 0
d MAX ? V IN ? F LC
C2
R2 = ---------------------------------------------
(EQ. 4)
COMP
R2
C1
R3
C3
2. Calculate C1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
-
desired number). The higher the quality factor of the output
E/A
+
FB
Ro
R1
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
C1 = ------------------------------------------------
VREF
1
2 π ? R2 ? 0.5 ? F LC
(EQ. 5)
C2 = ---------------------------------------------------------
PWM
OSCILLATOR
V OSC
V IN
V OUT
3. Calculate C2 such that F P1 is placed at F CE .
C1
2 π ? R2 ? C1 ? F CE – 1
(EQ. 6)
CIRCUIT
UGATE
L
D
4. Calculate R3 such that F Z2 is placed at F LC . Calculate C3
such that F P2 is placed below F SW (typically, 0.5 to 1.0
HALF-BRIDGE
times F SW ). F SW represents the switching frequency.
DRIVE
PHASE
LGATE
C
E
Change the numerical factor to reflect desired placement
of this pole. Placement of F P2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R3 = ----------------------
F SW
C3 = -------------------------------------------------
ISL6545x EXTERNAL CIRCUIT
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
R1
------------ – 1
F LC
1
2 π ? R3 ? 0.7 ? F SW
(EQ. 7)
COMPENSATION DESIGN
It is recommended a mathematical model is used to plot the
F LC = ---------------------------
F CE = ------------------------
d MAX ? V IN 1 + s ( f ) ? E ? C
G MOD ( f ) = ------------------------------ ? ----------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( E + D ) ? C + s ( f ) ? L ? C
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a DC
gain, given by d MAX V IN /V OSC , and shaped by the output
filter, with a double pole break frequency at F LC and a zero at
F CE . For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
1 1
2 π ? L ? C 2 π ? C ? E (EQ. 3)
loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
adjust as necessary. The equations shown in Equations 8
and 9 describe the frequency response of the modulator
(G MOD ), feedback compensation (G FB ) and closed-loop
response (G CL ):
2
G FB ( f ) = ------------------------------------------------------ ?
? -----------------------------------------------------------------------------------------------------------------------------
( 1 + s ( f ) ? R3 ? C3 ) ? ? 1 + s ( f ) ? R2 ? ? ---------------------- ? ?
The compensation network consists of the error amplifier
(internal to the ISL6545x) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
1 + s ( f ) ? R2 ? C1
s ( f ) ? R1 ? ( C1 + C2 )
1 + s ( f ) ? ( R1 + R3 ) ? C3
C1 ? C2
? ? C1 + C2 ? ?
(EQ. 8)
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F 0dB and 180°. The
G CL ( f ) = G MOD ( f ) ? G FB ( f )
where , s ( f ) = 2 π ? f ? j
equations that follow relate the compensation network’s poles,
COMPENSATION BREAK FREQUENCY EQUATIONS
F Z1 = --------------------------------
F P1 = -----------------------------------------------
2 π ? R2 ? ----------------------
F Z2 = ---------------------------------------------------
F P2 = --------------------------------
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 9. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R1 (1k Ω to 5k Ω , typically). Calculate
value for R2 for desired converter bandwidth (F 0 ). If
1
2 π ? R2 ? C1
1
2 π ? ( R1 + R3 ) ? C3
1
C1 ? C2
C1 + C2
1
2 π ? R3 ? C3
(EQ. 9)
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 9, the design procedure can
be followed as presented.
11
FN6305.6
March 3, 2011
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