参数资料
| 型号： | ISL6545IBZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 8-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6545IBZ-TDKR |
ISL6545, ISL6545A
time it will pull the output voltage down to the final value. Any
resistive load connected to the output will help pull down the
voltage (at the RC rate of the R of the load and the C of the
output capacitance).
V OUT OVERCHARGED
V OUT PRE-BIASED
Following POR (and 6.8ms delay), the ISL6545x initiates the
Overcurrent Protection sample and hold operation. The
LGATE driver is disabled to allow an internal 21.5μA current
source to develop a voltage across R OCSET . The ISL6545x
samples this voltage (which is referenced to the GND pin) at
the LGATE/OCSET pin, and holds it in a counter and DAC
combination. This sampled voltage is held internally as the
Overcurrent Set Point, for as long as power is applied, or
until a new sample is taken after coming out of a shut-down.
The actual monitoring of the lower MOSFET’s on-resistance
starts 200ns (nominal) after the edge of the internal PWM
logic signal (that creates the rising external LGATE signal).
This is done to allow the gate transition noise and ringing on
the PHASE pin to settle out before monitoring. The
monitoring ends when the internal PWM edge (and thus
GND>
V OUT NORMAL
LGATE) goes low. The OCP can be detected anywhere
within the above window.
t0
t1
t2
If the regulator is running at high UGATE duty cycles (around
FIGURE 3. SOFT-START WITH PRE-BIAS
If the V IN to the upper MOSFET drain is from a different
supply that comes up after V CC , the soft-start would go
through its cycle, but with no output voltage ramp. When V IN
turns on, the output would follow the ramp of the V IN (at
close to 100% duty cycle, with COMP/SD pin >4V), from
zero up to the final expected voltage. If V IN is too fast, there
may be excessive inrush current charging the output
capacitors (only the beginning of the ramp, from zero to
V OUT matters here). If this is not acceptable, then consider
changing the sequencing of the power supplies, or sharing
the same supply, or adding sequencing logic to the
COMP/SD pin to delay the soft-start until the V IN supply is
ready (see “Input Voltage Considerations” on page 9).
If the IC is disabled after soft-start (by pulling COMP/SD pin
low), and then enabled (by releasing the COMP/SD pin),
then the full initialization (including OCP sample) will take
place. However, that there is no new OCP sampling during
overcurrent retries.
If the output is shorted to GND during soft-start, the OCP will
handle it, as described in the next section.
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a
shorted output by using the lower MOSFET’s on-resistance,
r DS(ON) , to monitor the current. A resistor (R OCSET )
programs the overcurrent trip level (see “Typical Application”
and reduces cost by eliminating a current sensing resistor. If
overcurrent is detected, the output immediately shuts off, it
cycles the soft-start function in a hiccup mode (2 dummy
soft-start time-outs, then up to one real one) to provide fault
protection. If the shorted condition is not removed, this cycle
will continue indefinitely.
7
75% for 600kHz or 87% for 300kHz operation), then the
LGATE pulse width may not be wide enough for the OCP to
properly sample the r DS(ON) . For those cases, if the LGATE
is too narrow (or not there at all) for 3 consecutive pulses,
then the third pulse will be stretched and/or inserted to the
425ns minimum width. This allows for OCP monitoring every
third pulse under this condition. This can introduce a small
pulse-width error on the output voltage, which will be
corrected on the next pulse; and the output ripple voltage will
have an unusual 3-clock pattern, which may look like jitter.
This is not necessarily a problem; it is more of a compromise
to maintain OCP at the higher duty cycles. If the OCP is
disabled (by choosing a too-high value of R OCSET , or no
resistor at all), then the pulse stretching feature is also
disabled. Figure 4 illustrates the LGATE pulse width
stretching, as the width gets smaller.
> 425 ns
= 425 ns
< 425 ns
<< 425 ns
FIGURE 4. LGATE PULSE STRETCHING
FN6305.6
March 3, 2011
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