参数资料
| 型号： | ISL6566CR |
| 厂商： | Intersil |
| 文件页数： | 12/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
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ISL6566
Output Voltage Setting
The ISL6566 accommodates three different DAC ranges:
PWM
I L
SWITCHING PERIOD
I SEN
SAMPLING PERIOD
The ISL6566 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at the
VID pins. The DAC decodes the 5 or 6-bit logic signals into
one of the discrete voltages shown in Tables 2, 3, and 4.
Each VID pin is pulled up to an internal 1.2V voltage by a
weak current source (40 μ A current), which decreases to 0 as
the voltage at the VID pin varies from 0 to the internal 1.2V
pull-up voltage. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
.
Intel VRM9.0, AMD Hammer, or Intel VRM10.0. The state of
the VRM10 and VID12.5 pins decide which DAC version is
OLD SAMPLE
CURRENT
NEW SAMPLE
CURRENT
active. Refer to Table 1 for a description of how to select the
desired DAC version.
TIME
FIGURE 4. SAMPLE AND HOLD TIMING
TABLE 1. ISL6566 DAC SELECT TABLE
DAC VERSION VRM10 PIN VID12.5 PIN
The ISL6566 supports MOSFET r DS(ON) current sensing to
sample each channel’s current for channel-current balance.
The internal circuitry, shown in Figure 5 represents channel
n of an N-channel converter. This circuitry is repeated for
VRM10.0
VRM9.0
AMD HAMMER
high
low
low
-
high
low
each channel in the converter, but may not be active
depending on the status of the PVCC3 and PVCC2 pins, as
described in the PWM Operation section.
TABLE 2. AMD HAMMER VOLTAGE IDENTIFICATION CODES
VID4
VID3
VID2
VID1
VID0
VDAC
V IN
1
1
1
1
1
Off
I SEN = I ------------------------- ) -
DS ( ON
L R
I n
r
ISEN
CHANNEL N
UPPER MOSFET
1
1
1
1
1
1
1
0
0
1
0.800
0.825
SAMPLE
&
HOLD
-
+
ISL6565A INTERNAL CIRCUIT
I L
ISEN(n)
R ISEN
-
I L r DS ( ON )
+
CHANNEL N
LOWER MOSFET
EXTERNAL CIRCUIT
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0.850
0.875
0.900
0.925
0.950
0.975
1.000
FIGURE 5. ISL6566 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
The ISL6566 senses the channel load current by sampling
the voltage across the lower MOSFET r DS(ON) , as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL6566, is connected to the PHASE node through a
resistor, R ISEN . The voltage across R ISEN is equivalent to
the voltage drop across the r DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I L . The ISEN current is
sampled and held as described in the Current Sampling
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
I n = I L ---------------------- )
section. From Figure 5, the following equation for I n is
derived where I L is the channel current.
r DS ( ON
R ISEN
(EQ. 3)
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
1.250
1.275
1.300
12
FN9178.4
March 9, 2006
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