参数资料
| 型号： | ISL6566CR |
| 厂商： | Intersil |
| 文件页数： | 22/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页
ISL6566
PVCC
C GD
D
V IN
CHANNEL N
UPPER MOSFET
R HI2
R LO2
LGATE
G
R G2
R GI2
C GS
C DS
Q2
ISEN(n)
R ISEN
I L
S
-
L DS ( ON )
ISL6566
+
I
r
R ISEN = ----------------------- )
r DS ( ON I FL (EQ. 24)
--------
N
50 × 10 6
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P DR_UP , the lower drive path resistance,
P DR_UP , and in the boot strap diode, P BOOT . The rest of the
power will be dissipated by the external gate resistors (R G1
and R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P DR , can be roughly
estimated as:
CHANNEL N
LOWER MOSFET
FIGURE 17. ISL6566 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY
Select values for these resistors based on the room
temperature r DS(ON) of the lower MOSFETs; the full-load
operating current, I FL ; and the number of phases, N using
Equation 24.
–
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components of
one or more channels are inhibited from effectively dissipating
P BOOT = ---------------------
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
P Qg_Q1
3
(EQ. 23)
their heat so that the affected channels run hotter than
desired, choose new, smaller values of R ISEN for the affected
phases (see the section entitled Channel-Current Balance ).
Choose R ISEN,2 in proportion to the desired decrease in
temperature rise in order to cause proportionally less current
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1
R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2
R LO2 + R EXT2 ?
R EXT2 = R G2 + -------------
R EXT1 = R G1 + -------------
N Q2
N
? T
R ISEN , 2 = R ISEN ---------- 2
? R HI1 R LO1 ? P Qg_Q1
3
? R HI2 R LO2 ? P Qg_Q2
2
R GI1 R GI2
Q1
Current Balancing Component Selection
The ISL6566 senses the channel load current by sampling
the voltage across the lower MOSFET r DS(ON) , as shown in
Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and
ISEN3. The resistors connected between these pins and the
respective phase nodes determine the gains in the channel-
current balance loop.
22
to flow in the hotter phase.
(EQ. 25)
? T 1
In Equation 25, make sure that ? T 2 is the desired temperature
rise above the ambient temperature, and ? T 1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 25 is usually
sufficient, it may occasionally be necessary to adjust R ISEN
two or more times to achieve optimal thermal balance
between all channels.
Load Line Regulation Component Selection (DCR
Current Sensing)
For accurate load line regulation, the ISL6566 senses the
total output current by detecting the voltage across the
output inductor DCR of each channel (As described in the
Load Line Regulation section). As Figure 18 illustrates, an
R-C network is required to accurately sense the inductor
DCR voltage and convert this information into a “droop”
voltage, which is proportional to the total output current.
Choosing the components for this current sense network is a
two step process. First, R COMP and C COMP must be
chosen so that the time constant of this R COMP -C COMP
network matches the time constant of the inductor L/DCR.
FN9178.4
March 9, 2006
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