参数资料
型号: ISL6566CR
厂商: Intersil
文件页数: 25/29页
文件大小: 0K
描述: IC CTRLR PWM BUCK 3PHASE 40-QFN
标准包装: 50
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.8 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6566
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than ? V MAX . This
places an upper limit on inductance.
Equation 32 gives the upper limit on L for the cases when the
Input Capacitor Selection
The input capacitors are responsible for sourcing the ac
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 33
addresses the leading edge. Normally, the trailing edge dictates
0.3
I L,PP = 0
I L,PP = 0.25 I O
I L,PP = 0.5 I O
I L,PP = 0.75 I O
the selection of L because duty cycles are usually less than
50%. Nevertheless, both inequalities should be evaluated, and
L should be selected based on the lower of the two results. In
each equation, L is the per-channel inductance, C is the total
output capacitance, and N is the number of active channels.
0.2
L ≤ --------------------------------- ? V MAX – ( ? I ? ESR )
2 ? N ? C ? V O
( ? I ) 2
(EQ. 32)
0.1
L ≤ ---------------------------------- ? V MAX – ( ? I ? ESR ) ? V IN – V O ?
( ? I ) 2
( 1.25 ) ? N ? C
Switching Frequency
? ?
(EQ. 33)
0
0
0.2
0.4 0.6
DUTY CYCLE (V IN/ V O )
0.8
1.0
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
MOSFETs , and they establish the upper limit for the switching
frequency. The lower limit is established by the requirement for
fast transient response and small output-voltage ripple as
outlined in Output Filter Design . Choose the lowest switching
frequency that allows the regulator to meet the transient-
response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R T . Figure 21 and Equation 34 are
provided to assist in selecting the correct value for R T .
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
For a three-phase design, use Figure 22 to determine the input-
capacitor RMS current requirement set by the duty cycle,
maximum sustained output current (I O ), and the ratio of the
peak-to-peak inductor current (I L,PP ) to I O . Select a bulk
capacitor with a ripple current rating which will minimize the
total number of input capacitors required to support the RMS
current calculated. The voltage rating of the capacitors should
also be at least 1.25 times greater than the maximum input
voltage. Figures 23 and 24 provide the same input RMS current
information for two-phase and single-phase designs
R T = 10
[ 10.61 – 1.035 log ( f S ) ]
(EQ. 34)
respectively. Use the same approach for selecting the bulk
capacitor type and number.
1000
0.3
0.2
100
0.1
I L,PP = 0
10
10
100 1000
SWITCHING FREQUENCY (kHz)
10000
0
0
I L,PP = 0.5 I O
I L,PP = 0.75 I O
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V IN/ V O )
FIGURE 21. R T vs SWITCHING FREQUENCY
25
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
FN9178.4
March 9, 2006
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