参数资料
| 型号： | ISL6566CR |
| 厂商： | Intersil |
| 文件页数： | 16/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
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ISL6566
VDIFF
Dynamic VID
Modern microprocessors need to make changes to their core
+
V OFS
-
R FB
VREF
E/A
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
FB
I OFS
DAC inputs and respond to on-the-fly VID changes in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption.
The DAC mode the ISL6566 is operating in determines how
the controller responds to a dynamic VID change. When in
VRM10 mode the ISL6566 checks the VID inputs six times
every switching cycle. If a new code is established and it
R OFS
OFS
ISL6566
+
-
0.5V
-
+
1.5V
stays the same for 3 consecutive readings, the ISL6566
recognizes the change and increments the reference.
Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or
decrementing one VID step at a time. In VRM10 setting, the
GND
GND
VCC
ISL6566 will immediately change the reference to the new
requested value as soon as the request is validated; in
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VDIFF
cases where the reference step is too large, the sudden
change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VRM10 VID change, a VID step change smoothing
network is required for an ISL6566 based voltage regulator.
-
V OFS
+
R FB
FB
VREF
E/A
This network is composed of a 1k ? internal resistor between
the output of DAC and the capacitor C REF , between the REF
pin and ground. The selection of C REF is based on the time
duration for 1 bit VID change and the allowable delay time.
I OFS
Assuming the microprocessor controls the VID change at 1
bit every T VID , the relationship between C REF and T VID is
given by Equation 10.
C REF = 0.004X T VID
(EQ. 10)
VCC
As an example, for a VID step change rate of 5 μ s per bit, the
R OFS
+
-
+
1.5V
value of C REF is 22nF based on Equation 10.
When running in VRM9 or AMD Hammer operation, the
OFS
ISL6566
-
GND
0.5V
VCC
ISL6566 responds slightly different to a dynamic VID change
than when in VRM10 mode. In these modes the VID code can
be changed by more than a 1-bit step at a time. Once the
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
controller receives the new VID code it waits half of a phase
cycle and then begins slewing the DAC 12.5mV every phase
cycle, until the VID and DAC are equal. Thus, the total time
required for a VID change, t DVID , is dependent on the switching
frequency (f S ), the size of the change ( ? V VID ), and the time
required to register the VID change. The one-cycle addition in
0.5 × R FB
V OFFSET
1.5 × R FB
V OFFSET
t DVID = ----- ? ------------------ + 1.5 ?
f S ? 0.0125
For Positive Offset (connect R OFS to GND):
R OFS = --------------------------
For Negative Offset (connect R OFS to VCC):
R OFS = --------------------------
16
(EQ. 8)
(EQ. 9)
the t DVID equation is due to the possibility that the VID code
change may occur up to one full switching cycle before being
recognized. The approximate time required for a ISL6566-
based converter in AMD Hammer configuration running at f S =
335kHz to make a 1.1V to 1.5V reference voltage change is
about 100 μ s, as calculated using the following equation.
1 ? V VID (EQ. 11)
?
FN9178.4
March 9, 2006
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