参数资料
型号: ISL8126IRZ
厂商: Intersil
文件页数: 22/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 60
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 5.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL8126
Typical Performance Curves
35
33
31
29
27
(Continued)
35
33
31
29
27
25
-50
-25
0
25
50
75
100
125
150
25
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
FIGURE 7. EN/VFF1 HYSTERESIS CURRENT vs TEMPERATURE
Modes of Operation
There are 9 typical operation modes depending upon the signal
levels on EN/VFF1, EN/VFF2, VSEN2+, VSEN2-, FB2, and
CLKOUT/REFIN.
MODE 1: The IC is completely disabled when EN/VFF1 and
EN/VFF2 are pulled below 0.8V.
MODE 2: With EN/VFF1 pulled low and EN/VFF2 pulled >0.8V
(Mode 2A), or EN/VFF1 pulled >0.8V and EN/VFF2 pulled low
(Mode 2B), the ISL8126 operates as a single phase regulator.
When EN/VFF1 is pulled low, the ISHARE pin is pulled to VCC
internally. Upon EN/VFF1 >0.8V, there will be current sourcing
out from the ISHARE pin, which represents the Channel 1 current
plus 15μA offset current.
MODE 3: When VSEN2- is used as a negative sense line, both
channels’ phase shift depends upon the voltage level of
CLKOUT/REFIN. When the CLKOUT/REFIN pin is within 29% to
45% of VCC, Channel 2 delays 0° over Channel 1 (Mode 3A);
when within 45% to 62% of VCC, there is a 90°delay (Mode 3B);
when greater than 62% to VCC, there is a 180° delay (Mode 3C).
MODE 4: When VSEN2- is used as a negative remote sense line,
and CLKOUT/REFIN is connected to an external voltage ramp
lower than the internal soft-start ramp and lower than 0.6V, the
external ramp signal will replace Channel 2’s internal soft-start
ramp to be tracked at start-up, controller operating in DDR mode.
The controller will use the lowest voltage among the internal 0.6V
reference, the external voltage in CLKOUT/REFIN pin and the
soft-start ramp signal. Channel 1 is delayed 60° behind
Channel 2. Refer to the DDR and Dual Mode Operation on
MODE 5: With VSEN2- pulled within 400mV of VCC, FB2 pulled to
ground and VSEN2+ pulled either to VCC or GND, the internal
channels are 180° out-of-phase and operate in 2-phase single
output (Mode 5A). The CLKOUT/REFIN pin also signals out clock
with 60° phase shift (rising edge) relative to the Channel 1’s
clock signal (falling edge of PWM) for 6-phase operation with two
other ISL8126s (Mode 5B). When the share pins are not
connected to each other for the three ICs in sync, two of which
22
TEMPERATURE (°C)
FIGURE 8. EN/VFF2 HYSTERESIS CURRENT vs TEMPERATURE
can operate in Mode 5A. The 3rd IC can be operated in Mode 3 to
generate 3 independent outputs (Mode 5C), or the 3rd IC can
also be operated in Mode 4 to generate 4 independent outputs
(Mode 5D).
MODE 6: With VSEN2- pulled within 400mV of VCC, FB2 pulled to
VCC and VSEN2+ pulled to GND, the internal channels (as 1st and
3rd Phase, respectively) are 240° out-of-phase. The
CLKOUT/REFIN pin signals out 120° relative phases to the falling
edge of Channel 1’s clock signal to synchronize with the second
ISL8126’s Channel 1 (as 2nd Phase). This allows 3-phase single
output configuration to be constructed using two ISL8126s.
MODE 7: With VSEN2- pulled within 400mV of VCC and both of
FB2 and VSEN2+ pulled to VCC, the internal channel is 180°
out-of-phase. The CLKOUT/REFIN pin signals out (rising edge)
90° relative phase to the Channel 1’s clock signal (falling edge of
PWM) to synchronize with another ISL8126, which can operate
at Mode 3, 4, 5A, or 7A. A 4-phase single output converter can be
constructed with two ISL8126s operating in Mode 5A or 7A
(Mode 7A). If the share bus is not connected between ICs, each IC
could generate an independent output (Mode 7B). When the
second ISL8126 operates as two independent regulators
(Mode 3) or in DDR mode (Mode 4), then a three independent
output system is generated (Mode 7C). Both ICs can also be
constructed as a 3-phase converter (0°, 90°, and 180°, not an
equal phase shift for 3-phase) with a single phase regulator
(270°).
MODE 8: The output CLKOUT signal allows expansion for
12-phase operation with the cascaded sequencing, as shown in
Table 2. No external clock is required in this mode for the desired
phase shift.
MODE 9: With an external clock, the part can be expanded for 5,
7, 8, 9 10 and 11 phase single output operation with the desired
phase shift.
FN7892.1
August 16, 2012
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