参数资料
型号: ISL8126IRZ
厂商: Intersil
文件页数: 27/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 60
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 5.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL8126
EN/VFF1
0.8V
+
-
EN1
EN/VFF2
0.8V
+
-
EN2
VMON1
113%
VMON1
V REF
+
-
PGOOD1
87%
EN/VFF1
OR
AND
FORCE
LGATE1
HIGH
CH1 SOFT-START DONE
VMON1>120%
VMON2
+
OR
V REF
-
PGOOD2
VMON2
MULTIPHASE
MODE = HIGH
AND
CH2 SOFT-START DONE
113%
EN1
PGOOD1
PGOOD
87%
EN/VFF2
VMON2 > 120%
OR
AND
FORCE
LGATE2
HIGH
EN2
PGOOD2
PGOOD1
PGOOD2
+20%
FIGURE 17. FORCE LGATE HIGH LOGIC
There is another non-latch OV protection (113% of target level).
At the condition of EN/VFF low and the output over 113% OV, the
lower side MOSFET will turn on until the output drops below 87%.
This is to protect the overall power trains in case of only one
channel of a multiphase system detecting OV. The low-side
MOSFET always turns on at the conditions of EN/VFF = LOW and
the output voltage above 113% (all VMON pins and EN/VFF pins
VMON1, 2
PGOOD1, 2
+13%
+9%
V REF
-9%
-13%
PGOOD LATCH OFF
AFTER 120% OV
are tied together) and turns off after the output drops below 87%.
Thus, in a high phase count application (Multiphase Mode), all
cascaded ICs can latch off simultaneously via the EN/VFF pins
(EN/VFF pins are tied together in multiphase mode), and each IC
shares the same sink current to reduce the stress and eliminate
the bouncing among phases.
The UV functionality is not enabled until the end of soft-start. In a
UV event, if the output drops below -13% of the target level due to
some reason (cases when EN/VFF is not pulled low) other than
OV, OC, OT, and PLL faults, the lower MOSFETs will be turned on
for ~345ns for each switching cycle to avoid high negative
voltage ringing until the UN condition is removed.
FIGURE 16. POWER-GOOD THRESHOLD WINDOW
Overvoltage and Undervoltage Protection
VOUT
120%
The Overvoltage (OV) and Undervoltage (UV) protection circuitry
monitor the voltage on the VMON pins.
OV protection is active upon VCC POR. An OV condition (>120%)
3 CYCLES
3 CYCLES
would latch IC off (the high-side MOSFET to latch off
permanently; the low-side MOSFET turns on immediately at the
PGOOD
UV
OV LATCH
time of OV trip and then turns off after the VMON drops below
87%). The EN/VFF and PGOOD are also latched low at OV event.
The latch condition can be reset only by recycling VCC. In
Dual/DDR mode, each channel is responsible for its own OV
event with the corresponding VMON as the monitor. In
multiphase mode, both channels respond simultaneously when
either triggers an OV event.
27
UGATE AND EN/VFF LATCH LOW
FIGURE 18. PGOOD TIMING UNDER UV AND OV
FN7892.1
August 16, 2012
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