参数资料
| 型号： | ISL8126IRZ |
| 厂商： | Intersil |
| 文件页数： | 26/39页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 60 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 5.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页
ISL8126
VIN
FIRST PWM PULSE
SS Settling at VREF + 100mV
ISL8126
2-PHASE
EN/VFF1
R UP
ISL8126
2-PHASE
EN/VFF1
0.0V
VMON
= --------------
SW
EN/VFF2
EN/VFF2
-100mV
t
SS
1280
F
EN_HYS
EN_HYS
PHASE
192
= --------------
SW
R
UP
V
= ------------------------------------------------------------
I T N
R DOWN
t
SS_DLY
F
FIGURE 12. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
FIGURE 13. SOFT-START WITH VOUT = 0V
Voltage Feed-forward
Other than used as a voltage monitor described in the previous
section, the voltages applied to the EN/VFF pins are also fed to
adjust the amplitude of each channel’s individual sawtooth. This
FIRST PWM PULSE
Pre-charged level
SS Settling at VREF + 100mV
VMON
helps to maintain a constant gain ( G M = VIN ? D MAX ? Δ V RAMP )
contributed by the modulator and the input voltage to achieve
optimum loop response over a wide input voltage range. The
amplitude of each channel’s sawtooth is set to 1.25 times the
corresponding EN/VFF voltage upon its enable (above 0.8V). The
sawtooth ramp offset voltage is 1V, and the peak of the sawtooth
is limited to VCC - 1.4V. This allows a maximum peak-to-peak
amplitude of sawtooth ramp to be VCC - 2.4V. A constant voltage
(0.8V) is fed into the ramp generator to maintain a minimum
peak-to-peak ramp.
With VCC = 5.4V, the ramp has an allowable maximum
peak-to-peak voltage of 3V and minimum of 1V. Therefore, the
feed-forward voltage effective range is typically 3x.
A 192 cycle delay is added after the system reaches its rising
POR and prior to the soft-start. The RC timing at the EN/VFF pin
should be sufficiently small to ensure that the input bus reaches
its static state and the internal ramp circuitry stabilizes before
soft-start. A large RC could cause the internal ramp amplitude
not to synchronize with the input bus voltage during output
start-up or when recovering from faults. It is recommended to
use open drain or open collector to gate this pin for any system
delay, as shown in Figure 11.
Soft-start
The ISL8126 has two independent digital soft-start circuitry with
fixed 1280 switching cycles. Refer to Figure 13. The full soft-start
time from 0V to the target value can be estimated using
Equation 1.
-100mV
FIGURE 14. SOFT-START WITH OUTPUT PRE-CHAREGED LEVEL <
FINAL TARGET LEVEL
OV = 113%
FIRST PWM PULSE
VOUT TARGET VOLTAGE
FIGURE 15. SOFT-START WITH VOUT BELOW OV BUT ABOVE
FINAL TARGET VOLTAGE
Power-Good
Both channels share the same PGOOD output. Either of the
channels indicating out-of-regulation will pull-down the PGOOD
pin. The Power-Good comparators monitor the voltages on the
VMON pins. The trip points are shown in Figure 16. States of both
EN/VFF1 and EN/VFF2 have impact on the PGOOD signal. If one
of the VMON pins’ voltage is out of the threshold window, PGOOD
will not pull low until the fault presents for three consecutive
clock cycles.
t SS = --------------
1280
f SW
(EQ. 1)
The ISL8126 has the ability to work under a pre-charged output
(see Figure 14). The output voltage would not be yanked down
during pre-charged start-up. If the pre-charged output voltage is
greater than the final target level but lowered to 120% setpoint,
the switching will not start until the FB voltage reduces to the
internal soft-start signal or the end of the soft-start is declared
(see Figure 15).
26
FN7892.1
August 16, 2012
相关PDF资料 |
PDF描述 |
|---|---|
| ISL8130IAZ | IC REG CTRLR BST FLYBK VM 20QSOP |
| ISL85001IRZ-T | IC REG BUCK ADJ 1A 12DFN |
| ISL8500IRZ-T | IC REG BUCK ADJ 2A 12DFN |
| ISL8502AIRZ | IC REG BUCK SYNC ADJ 2A 24QFN |
| ISL8502IRZ | IC REG BUCK SYNC ADJ 2.5A 24QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8126IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126IRZ-T7A | 制造商:Intersil Corporation 功能描述:SCALABLE 2-PHASE CONTROLLER W/INTEGRATED DRIVERS, IND, 32LD - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN |
| ISL8126IRZ-TK | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8128IAZ-TK | 制造商:Intersil Corporation 功能描述:PB-FREE SYNC BUCK PWM CONT. W/ 4.5V-28V |
| ISL8130 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Single Universal Pulse-Width Modulation (PWM) Controller |
发布紧急采购，3分钟左右您将得到回复。