参数资料
| 型号： | ISL8126IRZ |
| 厂商： | Intersil |
| 文件页数： | 30/39页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-QFN |
| 标准包装： | 60 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 90% |
| 电源电压： | 3 V ~ 5.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL8126
exceeded during the soft-start interval, the controller pulls
EN/VFF low again. The PGOOD signal will remain low and the
soft-start interval will be allowed to expire. Another soft-start
interval will be initiated after the delay interval. If an overcurrent
trip occurs again, this same cycle repeats until the fault is
removed.
The OCP function is enabled at start-up. The ISL8126 monitors 2
signals: sampled channel current, ICS, and ISHARE voltage for
overcurrent protection.
CHANNEL CURRENT OCP
Each sampled channel current, I CS , is compared to 111μA (typ.)
for the OCP trip point. The channel over current trip point can be
set by using R ISEN value such that the over current trip point
corresponds to the channel sensing current, ICS, of 111μA. For
DCR current sensing, Equation 7, and r DS(ON) current sensing,
Equation 9, the R ISEN can be estimated from Equations 10 and
11, respectively.
In multiphase operation, the VISHARE represents the average
current of all ISL8126 and compares with the ISHARE pin precision
1.2V threshold to determine the overcurrent condition. At the same
time, each channel has additional overcurrent trip point at 111μA
with 7-cycle delay for channel overcurrent protection. This scheme
helps protect against loss of channel(s) in multi-phase mode so that
no single channel could carry excessive current in such event. With
R ISHARE = 10k Ω, It would make the channel current OCP and
ISHARE OCP trip at the same over current level; (111μA + 15μA) x
10k Ω = 1.26V.
Note that it is not necessary for the R ISHARE to be scaled to trip at
the same level as the 111μA OCP comparator if the application
allows. For instance, when Channel 1 operates independently, the
OC trip set by 1.2V comparator can be lower than 111μA trip point.
To set the ISHARE OCP in the multi-phase configuration, the R ISEN
must be determined first by using Equations 10 or 11. The IOC in
Equations 10 or 11 is overcurrent for each phase, which is
approximately IOC_total/number of phases. Upon determining
? IOC + ------------- ? ? ? --------------- – t MIN_OFF ? ? ? ? DCR
2F SW
? ?
R ISHARE = ------------------------------------------------------------------
? V OUT 1 – D ?
L
111 μ A
R ISEN = --------------------------------------------------------------------------------------------------------------
(EQ. 10)
R ISET , Equations 7, 8, 9, and 11 can be used to determine ISHARE
OCP, as shown in Equation 12.
1.2V
N CNTL
∑
( I AVG_CS + 15 μ A )
i
(EQ. 13)
? IOC + ------------- ? ? ? --------------- – t MIN_OFF ? ? ? ? r DS ( ON )
2F SW
?
?
(EQ. 12)
IAVG_CS = ---------------------------------
? V OUT 1 – D ?
L (EQ. 11)
111 μ A
R ISEN = ----------------------------------------------------------------------------------------------------------------------
Without temperature compensation, the OCP trip point should be
evaluated based on the DCR or MOSFET r DS(ON) values at the
maximum device’s temperature.
While configured as multi-phase operation (VSEN2- > VCC-
400mV), the channel OCP has 7 clock cycles delay before
entering hiccup mode.
In dual-output operation, the 7-clock cycle delay on Channel 2 is
bypassed so the circuit responds to over current condition
immediately. In this mode, the 7-clock cycle delay in Channel1 is
still active. The fast OCP response on Channel1 will be rely on the
OCP on ISHARE pin where the voltage on this pin represents the
Channel1 current.
During soft-start period with VMON1 less than 0.4V, the OCP
threshold on the sampled channel current, ICS, of both channels
are increased to 222μA (typ.) to compensate the in-rush current.
ISHARE OCP
Refer to the block diagram, ISHARE pin sources out a current
IAVG_CS with 15μA offset. In the 2-phase mode, IAVG_CS is the
average of both Channels 1 and 2 sampled currents as
calculated in Equation 12.
ICS1 + ICS2
2
While in the dual-output mode, IAVG_CS is a copy of channel1’s
sampled current.
30
i = 1
R ISET = R ISHARE ? N CNTL
where N CNTL is the number of the ISL8126 controllers in parallel
or multiphase operations.
For the R ISEN chosen for OCP setting, the final value is usually
higher than the number calculated from Equation 9. The reason
for which is practical, especially for low DCR applications since
the PCB and inductor pad soldering resistance would have large
effects in total impedance, affecting the DCR voltage to be
sensed.
Current Sharing Loop
When the ISL8126 operates in 2-phase mode (VSEN2- is pulled
within VCC - 400mV), the current control loop keeps Channel 1
and Channel 2 currents in balance. The sensed currents from
both channels are combined to create an average current
reference (IAVG), which represents average current of both
channel currents. The signal IAVG is then subtracted from the
individual sensed current (ICS1 or ICS2) to produce a current
correction signal for each channel. The block diagram of current
sharing control circuit is shown in Figure 22.
When both channels operate independently, the average
function is disabled, and the current correction block of
Channel 2 is also disabled. The I AVG_CS is Channel 1 sensed
current I CS1 . Channel 1 makes any necessary current correction
by comparing the voltages at ISET and ISHARE pins (for 3-phase,
two ISL8126s configuration).
When the share bus does not connect to other ICs, the ISET and
ISHARE pins can be shorted together and grounded via a single
resistor to ensure zero share error.
FN7892.1
August 16, 2012
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| ISL8126IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126IRZ-T7A | 制造商:Intersil Corporation 功能描述:SCALABLE 2-PHASE CONTROLLER W/INTEGRATED DRIVERS, IND, 32LD - Tape and Reel 制造商:Intersil Corporation 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN |
| ISL8126IRZ-TK | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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