参数资料
型号: ISL8126IRZ
厂商: Intersil
文件页数: 28/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 60
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 5.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL8126
PRE-POR Overvoltage Protection (PRE-POR-
INDUCTOR DCR SENSING
I ( s )
OVP)
V IN
L
CS ( n )
DCR
When both the VCC and PVCC are below PORs (not including EN
POR), the UGATE is low and LGATE is floating (high impedance).
EN/VFF has no control on LGATE when VCC and PVCC are below
their PORs. When VCC and PVCC are above their PORs, the LGATE
would not be floating but toggling with its PWM pulses. An
internal 10k Ω resistor, connected in between PHASE and LGATE
nodes, implements the PRE-POR-OVP circuit. The output of the
converter that is equal to phase node voltage via output
inductors is then effectively clamped to the low-side MOSFET’s
UGATE(n)
PHASE(n)
LGATE(n)
ISL8216
INTERNAL CIRCUIT
I
L
INDUCTOR
V L
V C (s)
R C
V OUT
C OUT
gate threshold voltage, which provides some protection to the
load if the upper MOSFET(s) is shorted during start-up, shutdown,
or normal operations. For complete protection, the low-side
MOSFET should have a gate threshold that is much smaller than
the maximum voltage rating of the load.
The PRE-POR-OVP works against pre-biased start-up when pre-
SAMPLE
&
HOLD
+
-
ISEN(n)A
ISEN(n)B
R ISEN(n)
(PTC)
R < -----------------------------------------------------------
V pre – biased ( max ) (EQ. 2)
V th ( min )
charged output voltage is higher than the threshold of the
low-side MOSFET, however, it can be disabled by placing a
resistor from LGATE to ground. The resistor value can be
estimated from Equation 2.
10k
------------------------------------------------- – 1
The resistor value should be as large as possible to minimize
power dissipation, while providing sufficient margin for the
internal 10k Ω and MOSFET’s Vth tolerances. For example, a 2k Ω
resistor is recommended for applications using logic-level
ISEN
FIGURE 19. DCR SENSING CONFIGURATION
An inductor’s winding is characteristic of a distributed resistance
as measured by the DCR (Direct Current Resistance) parameter.
Consider the inductor DCR as a separate lumped quantity, as
shown in Figure 19. The inductor current, I L ; will also pass
through the DCR. Equation 3 shows the s-domain equivalent
voltage across the inductor V L .
MOSFET with the maximum pre-biased voltage less than 5V.
V L = I L ? ( s ? L + DCR )
(EQ. 3)
? s ? ------------ + 1 ? ? ( DCR ? I )
V C = -----------------------------------------------------------------
Over-Temperature Protection (OTP)
When the junction temperature of the IC is greater than +150°C
(typically), both EN/VFF pins pull low to inform other cascaded
channels via their EN/VFF pins. All connected EN/VFFs stay low
and release after the IC’s junction temperature drops below
+125°C (typically), with a +25°C hysteresis (typical).
INDUCTOR CURRENT SENSING
The ISL8126 supports inductor DCR sensing, MOSFET’s r DS(ON)
sensing, or resistive sensing techniques. The circuits shown in
Figures 19, 20, and 21 represent one channel of the controller.
This circuitry is identical for both channels.
Note that the common mode input voltage range of the current
sense amplifiers is VCC - 1.8V. Therefore, the r DS(ON) sensing
must be used for applications with output voltage greater than
VCC - 1.8V. For example, when VCC = 5.4V, the inductor DCR and
the resistive sensing configurations can be used for output
voltage less than 3V. For higher output voltage, r DS(ON) sensing
configuration must be used.
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 19. The voltage on the capacitor V C ,
can be shown to be proportional to the inductor current I L , see
Equation 4.
L
? DCR ? L (EQ. 4)
( s ? RC + 1 )
If the R-C network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor V C is equal to the
voltage drop across the DCR, i.e. proportional to the inductor
current. The value of R should be as small as feasible for best
signal-to-noise ratio. Make sure the resistor package size is
appropriate for the power dissipated and include this loss in
efficiency calculations. In calculating the minimum value of R,
the average voltage across C (which is the average I L DCR
product) is small and can be neglected. Therefore, the minimum
value of R may be approximated using Equation 5.
D ? ( V IN – max – V OUT ) + ( 1 – D ) ? V OUT
k ? P R – pkg ? δ P
2 2
R min = --------------------------------------------------------------------------------------------------------
(EQ. 5)
Where P R-pkg is the maximum power dissipation specification
for the resistor package and δ P is the derating factor for the
same parameter (eg.: P R-pkg = 0.063W for 0402 package,
δ P = 80% @ +85°C). k is the margin factor, also to limit
28
FN7892.1
August 16, 2012
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