参数资料
型号: ISL8126IRZ
厂商: Intersil
文件页数: 25/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 60
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 5.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL8126
Functional Description
Initialization
Initially, the ISL8126 Power-On Reset (POR) circuits continually
monitor the bias voltages (PVCC and VCC) and the voltage at the
EN/VFF pin. The POR function initiates soft-start operation 192
clock cycles after the following conditions are met:
? VCC and PVCC voltages exceed their POR thresholds.
? PLL locking time has expired.
? EN/VFF pin voltage is pulled to be above 0.8V.
? For Channel 1 only, ISHARE voltage must fall below 70%
(typical) of VCC.
ISHARE is also pulled to VCC when Channel1 detects fault
conditions or EN/VFF1 is below its POR threshold. ISHARE is
released from VCC after EN/VFF1’s voltage higher than its POR
threshold for 16 switching cycles; therefore, there is 176 cycles
delay from ISHARE falls to 0.7*VCC to the beginning of soft start.
HIGH = ABOVE POR; LOW = BELOW POR
COMPARATOR
During shutdown or fault conditions, the soft-start is reset quickly
while UGATE and LGATE change states immediately (<100ns)
upon the input drop below falling POR. The soft-start initialization
circuit is shown in Figure 10.
The EN/VFF pin can be used as a voltage monitor and to set
desired hysteresis with an internal 30 μ A sinking current going
through an external resistor divider. The sinking current is
disengaged after the system is enabled. This feature is especially
designed for applications that require higher input rail POR for
better undervoltage protection. For example, in single-phase 12V
input applications, R UP = 53.6k and R DOWN = 5.23k will set the
turn-on threshold (V EN_RTH ) to 10.6V and turn-off threshold
(V EN_FTH ) to 9V, with 1.6V hysteresis (V EN_HYS ).
There is an internal transistor, which will pull down the EN/VFF
pin under fault conditions. The multiphase system can
immediately turn off all ICs under fault conditions of one or more
phases by pulling all EN/VFF pins low. Thus, no bouncing occurs
among channels at fault and no single phase could carry all
current and be over stressed. The pull-up resistor (R UP ) should be
scaled to sink no more than 5mA current to the EN/VFF pin.
Essentially, the EN/FF pins cannot be directly connected to VCC.
0.7*VCC
ISHARE
+
-
VCC POR
PVCC POR
EN/VFF1 POR
AND
176
Cycles
SOFT-START
OF CHANNEL 1
PLL LOCKING
SOFT-START
VCC POR
PVCC POR
AND
192
Cycles
OF CHANNEL 2
EN/VFF2 POR
FIGURE 10. SOFT-START INITIALIZATION LOGIC
Nx I EN_HYS
V EN_FTH – V EN_REF
V EN_HYS
R UP = --------------------------------
R UP ? V EN_REF
R DOWN = -------------------------------------------------------
VCC
where N is number of EN/VFF pins connected together
G RAMP = 1.25
VCC - 1.4V
V
EN_FTH
= V
EN_RTH
– V
EN_HYS
UPPER LIMIT
= max (V CC_FF × G
Δ V
)
RAMP RAMP
V CC_FF = max(0.8V, V ENFF )
, VCC - 1.4V - V
RAMP_OFFSET
VIN
0.8V
V CC_FF
LIMITER
V RAMP_OFFSET = 1.0V
SAWTOOTH
AMPLITUDE
( Δ V RAMP )
LOWER LIMIT
(RAMP OFFSET)
0.8V
R UP
EN/VFF
EN_POR
SYSTEM DELAY
R DOWN
I EN_HYS = 30μA
OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/VFF1)
FIGURE 11. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
25
FN7892.1
August 16, 2012
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