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参数资料
| 型号： | LFX125EB-05F256C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 30/119页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 139K GATES 256-BGA |
| 标准包装： | 90 |
| 系列： | ispXPGA® |
| 逻辑元件/单元数： | 1936 |
| RAM 位总计： | 94208 |
| 输入/输出数： | 160 |
| 门数： | 139000 |
| 电源电压： | 2.3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FPBGA（17x17） |
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Lattice Semiconductor
ispXPGA Family Data Sheet
14
sysCLOCK PLL Description
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset, and feedback
signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are aligned
either at the board level or the device level.
The ispXPGA devices provide up to eight PLLs. Each PLL receives its input clock from its associated global clock
pin, and its output is routed to the associated global clock net. For example, PLL0 receives its clock input from the
GCLK0 global clock pin and provides output to the CLK0 global clock net. The PLL also has the ability to output a
secondary clock that is a division of the primary clock output. When using the secondary clock, the secondary
clock will be routed to the neighboring global clock net. For example, PLL0 will drive its primary clock output on the
CLK0 global clock net and its secondary clock output will drive the CLK1 global clock net. Additionally, each PLL
has a set of PLL_RST, PLL_FBK, and PLL_LOCK signals. The PLL_RST signal can be generated through routing
or a dedicated dual-function I/O pin. The PLL_FBK signal can be generated through a dedicated dual-function I/O
pin or internally from the Global Clock net associated with the PLL. The PLL_LOCK signal feeds routing directly
from the sysCLOCK PLL circuit. Figure 17 illustrates how the PLL_RST and PLL_FBK signals are generated.
Each PLL has four dividers associated with it, M, N, V, and K. The M divider is used to divide the clock signal,
while the N divider is used to multiply the clock signal. The V divider allows the VCO frequency to operate at
higher frequencies than the clock output, thereby increasing the frequency range. The K divider is only used when
a secondary clock output is needed. This divider divides the primary clock output and feeds to the adjacent global
clock net. Different combinations of these dividers allow the user to synthesize clock frequencies. Figure 16 shows
the ispXPGA PLL block diagram.
The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and
clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines of the
PLL. For more information on the PLL, please refer to TN1003, sysCLOCK PLL Usage and Design Guidelines.
Figure 16. ispXPGA PLL Block Diagram
GCLK_IN
PLL_RST
PLL_FBK
PLL_LOCK
CLK_OUT
Clock Net
Input Clock
(M) Divider
÷ 1 to 32
PLL (n)
Programmable
+Delay
--------------------
Programmable
-Delay
To Adjacent_PLL
Feedback
Divider (N)
X 1 to 32
Post-scalar
(V) Divider
÷
1, 2, 4, 8,
16, 32
Clock (K)
Divider
÷
2, 4, 8,
16, 32
From
Adjacent_PLL
SELECT
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LFX125EB-05F516C | 功能描述:FPGA - 现场可编程门阵列 139K 176 I/O ispJTAG RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFX125EB-05FH516C | 功能描述:FPGA - 现场可编程门阵列 Use LFX125EB-05F516C RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFX125EB-05FN256C | 功能描述:FPGA - 现场可编程门阵列 E-Ser139K Gt ispJTAG 2.5/3.3V -5 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFX125EB-05FN516C | 功能描述:FPGA - 现场可编程门阵列 E-Ser139K Gt ispJTA G 2.5/3.3V -5 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFX125EB-3F256C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ispXPGA Family |
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