参数资料
型号: LFX125EB-05F256C
厂商: Lattice Semiconductor Corporation
文件页数: 36/119页
文件大小: 0K
描述: IC FPGA 139K GATES 256-BGA
标准包装: 90
系列: ispXPGA®
逻辑元件/单元数: 1936
RAM 位总计: 94208
输入/输出数: 160
门数: 139000
电源电压: 2.3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 256-BGA
供应商设备封装: 256-FPBGA(17x17)
Lattice Semiconductor
ispXPGA Family Data Sheet
19
Configuration and Programming
The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of
memory, Static RAM and non-volatile E
2CMOS cells. The static RAM is used to control the functionality of the
device during normal operation and the E
2CMOS memory cells are used to load the SRAM. The E2CMOS memory
module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-
tion memory. There is a one-to-one relationship between SRAM memory and the E
2CMOS cells. The SRAM can
be configured either from the E
2CMOS memory or from an external source, as shown in Figure 21.
Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA
devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which
supports the IEEE 1149.1 Test Access Port (TAP) Std., accommodates bit-wide configuration. The sysCONFIG
port allows byte-wide configuration of the SRAM configuration memory. When programming the E
2CMOS memory,
only the 1149.1 TAP can be used.
Configuration and programming done through the 1149.1 Test Access Port (TAP) supports both the IEEE Std.
1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-System Configuration specification. To config-
ure or program the device using the 1149.1 TAP the device must be in the ISP mode. To configure the SRAM mem-
ory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM
memory can be configured either from the E
2CMOS memory or from an external source through the sysCONFIG
mode. Additionally, the SRAM can be re-configured from the E
2CMOS memory by executing a “REFRESH.” See
TN1026, ispXP Configuration Usage Guidelines, for more in depth information on the different programming
modes, timing and wake-up.
Figure 21. ispXP Block Diagram
Supports IEEE 1149.1 Boundary Scan Testability
All ispXPGA devices have boundary scan cells and supports the IEEE 1149.1 standard. This allows functional test-
ing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic
notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly
onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be
linked into a board-level serial scan path for more board level testing.
Security Scheme
A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed
SRAM
Memory Space
E2CMOS
Memory Space
sysCONFIG Peripheral Port
sysCONFIG
ISP 1149.1 TAP Port
Power-up
Refresh
Programming
in seconds
Download in
microseconds
Configuration
in milliseconds
Port
Mode
Memory Space
ISP
1532
BACKGND
SELECT
DEVICES
DISCONTINUED
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LFX125EB-3F256C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ispXPGA Family