参数资料
型号: LTC3731CG#TRPBF
厂商: Linear Technology
文件页数: 21/34页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 36-SSOP
标准包装: 2,000
系列: PolyPhase®
PWM 型: 电流模式
输出数: 1
频率 - 最大: 750kHz
占空比: 98.5%
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 36-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
LTC3731
APPLICATIONS INFORMATION
2.4V
C LP
DIGITAL
50k
t ON ( MIN ) <
R LP
PHASE 10k
DETECTOR/
OSCILLATOR
EXTERNAL
OSC OSC
PLLFLTR
PLLIN
PHASE/
FREQUENCY
DETECTOR
3731 F09
Figure 9. Phase-Locked Loop Block Diagram
the phase difference. Thus, the voltage on the PLLFLTR pin
is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operat-
ing point, the phase comparator output is open and the
filter capacitor C LP holds the voltage. The IC PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
ICs for a phase-locked system, the PLLFLTR pin of the
master oscillator should be biased at a voltage that will
guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 550kHz for 1.7V.
The loop filter components (C LP , R LP ) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C LP and R LP determine how fast the loop
acquires lock. Typically R LP =10k and C LP ranges from
0.01μF to 0.1μF.
Minimum On-Time Considerations
Minimum on-time, t ON(MIN) , is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may ap-
proach this minimum on-time limit and care should be
taken to ensure that:
V OUT
V IN ( f )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the IC will begin to skip every
other cycle, resulting in half-frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the minimum
on-time gradually increases. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that is low enough in
value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I OUT(MAX) at V IN(MAX) .
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V OUT shifts by
an amount equal to ? I LOAD ? ESR, where ESR is the ef -
fective series resistance of C OUT . ? I LOAD also begins to
charge or discharge C OUT , generating the feedback error
signal that forces the regulator to adapt to the current
change and return V OUT to its steady-state value. During
3731fc
21
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