参数资料
型号: LTC3839EUH#PBF
厂商: Linear Technology
文件页数: 26/50页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 1
频率 - 最大: 2MHz
电源电压: 4.5 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
LTC3839
APPLICATIONS INFORMATION
However, for 3.3V and other low voltage outputs, ad-
ditional circuitry is required to derive DRV CC power from
the converter output.
The following list summarizes the four possible connec-
tions for EXTV CC :
1. EXTV CC left open (or grounded). This will cause INTV CC
to be powered from the internal 5.3V LDO resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTV CC connected directly to switching converter output
V OUT is higher than the switchover voltage’s higher limit
(4.8V). This provides the highest efficiency.
3. EXTV CC connected to an external supply. If a 4.8V or
greater external supply is available, it may be used to
power EXTV CC providing that the external supply is
sufficient for MOSFET gate drive requirements.
4. EXTV CC connected to an output-derived boost network.
For 3.3V and other low voltage converters, efficiency
gains can still be realized by connecting EXTV CC to an
output-derived voltage that has been boosted to greater
than 4.8V.
For applications where the main input power never exceeds
5.3V, tie the DRV CC1 and DRV CC2 pins to the V IN input
through a small resistor, (such as 1Ω to 2Ω) as shown
in Figure 8 to minimize the voltage drop caused by the
gate charge current. This will override the LDO and will
prevent DRV CC from dropping too low due to the dropout
voltage. Make sure the DRV CC voltage exceeds the R DS(ON)
test voltage for the external MOSFET which is typically at
4.5V for logic-level devices.
LTC3839
Input Undervoltage Lockout (UVLO)
The LTC3839 has two functions that help protect the con-
troller in case of input undervoltage conditions. An internal
UVLO comparator constantly monitors the INTV CC and
DRV CC voltages to ensure that adequate voltages are pres-
ent. The comparator enables internal UVLO signal, which
locks out the switching action of both channels, until the
INTV CC and DR VCC1,2 pins are all above their respective
UVLO thresholds. The rising threshold (to release UVLO)
of the INTV CC is typically 4.2V, with 0.5V falling hysteresis
(to re-enable UVLO). The UVLO thresholds for DR VCC1,2 are
lower than that of INTV CC but higher than typical threshold
voltages of power MOSFETs, to prevent them from turning
on without sufficient gate drive voltages.
Generally for V IN > 6V, a UVLO can be set through monitoring
the V IN supply by using an external voltage divider at the
RUN pin from V IN to SGND. To design the voltage divider,
note that the RUN pin has two levels of threshold voltages.
The precision gate-drive-enable threshold voltage of 1.2V
can be used to set a V IN to turn on a channel’s switching.
If a resistor divider is used on the RUN pin, when V IN is
low enough and the RUN pin is pulled below the ~0.8V
threshold, the part will shut down all bias of INTV CC and
DRV CC and be put in micropower shutdown mode.
The RUN pin’s bias current depends on the RUN pin voltage.
The bias current changes should be taken into account
when designing the external voltage divider UVLO circuit.
An internal proportional-to-absolute-temperature (PTAT)
pull-up current source (~2.5μA at 25°C) is constantly con-
nected to this pin. When the RUN pin rises above 1.2V, the
TG and BG drives are enabled on and an additional 10μA
temperature-independent pull-up current is connected
internally to the RUN pin. Pulling the RUN pin below 1.2V
DRV CC2
DRV CC1
R DRVCC
C DRVCC
C IN
V IN
by more than an 80mV hysteresis turns off TG and BG,
and the additional 10μA pull-up current is disconnected.
3839 F08
Figure 8. Setup for V IN ≤ 5.3V
3839fa
26
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