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参数资料
| 型号： | LXT386LE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收发器|四|优税PCM-30/E-1 |的CMOS | QFP封装| 100引脚|塑料 |
| 文件页数： | 22/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT386LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
22
Datasheet
2.0
Functional Description
Figure 1 is a block diagram of the LXT384. The LXT384 is a fully integrated octal line interface
unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications.
Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive.
These two lines comprise a digital data loop for full duplex transmission.
The LXT384 can be controlled through hard-wired pins or by a microprocessor through a serial or
parallel interface (Host mode).
The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT384
is designed to operate without any reference clock when used as an analog front-end (line driver
and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All eight
clock recovery circuits share the same reference clock defined by the MCLK input signal.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 60%
of VCC. During power-up, an internal reset sets all registers to their default values and resets the
status and state machines for the LOS.
129
130
D5
C5
TTIP6
TRING6
AO
AO
Transmit Tip Output.
Transmit Ring Output.
131
C6, D6
TGND6
S
Transmit Driver Ground.
132
133
C7
D7
RTIP6
RRING6
AI
AI
Receive Tip Input.
Receive Ring Input.
134
A6, B6
TGND7
S
Transmit Driver Ground.
135
136
A5
B5
TRING7
TTIP7
AO
AO
Transmit Ring Output.
Transmit Tip Output.
137
A4, B4
TVCC7
S
Transmit Driver Power Supply.
138
139
B7
A7
RRING7
RTIP7
AI
AI
Receive Ring Input.
Receive Tip Input.
140
E4
LOS7
DO
Loss of Signal Output.
141
141
142
142
A3
A3
A2
A2
RNEG7
BPV7
RPOS7
RDATA7
DO
DO
DO
DO
Receive Negative Data Output.
Bipolar Violation Detect Output.
Receive Positive Data Output.
Receive Data Output.
143
A1
RCLK7
DO
Receive Clock Output.
144
144
B3
B3
TNEG7
UBS7
DI
DI
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
Table 1. LXT384 Pin Description (Sheet 12 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
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相关代理商/技术参数 |
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| LXT388LE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400 | 制造商:LVL1 制造商全称:LVL1 功能描述:All Rate Extended Range Switched 56/DDS Transceiver |
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| LXT441 | 制造商:LVL1 制造商全称:LVL1 功能描述:Switched 56/DDS Integrated DSU/CSU |
| LXT6155 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:155 Mbps SDH/SONET/ATM Transceiver |
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