参数资料
型号: LXT386LE
英文描述: PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
中文描述: 的PCM收发器|四|优税PCM-30/E-1 |的CMOS | QFP封装| 100引脚|塑料
文件页数: 63/80页
文件大小: 1112K
代理商: LXT386LE
Octal T1/E1/J1 Transceiver
LXT384
Datasheet
63
Figure 20. JTAG Timing
Table 47. Intel Mode Read Timing Characteristics
2
Parameter
Sym
Min.
Typ
1
Max
Unit
Test Conditions
Address setup time to latch
Tsalr
10
ns
Valid address latch pulse width
Tvl
30
ns
Latch active to active read setup time
Tslr
10
ns
Chip select setup time to active read
Tscsr
0
ns
Chip select hold time from inactive read
Thcsr
0
ns
Address hold time from inactive ALE
Thalr
5
ns
Active read to data valid delay time
Tprd
10
50
ns
Address setup time to RD inactive
Thar
1
ns
Address hold time from RD inactive
Tsar
5
ns
Inactive read to data tri-state delay time
Tzrd
3
35
ns
Valid read signal pulse width
Tvrd
60
ns
Inactive read to inactive INT delay time
Tint
10
ns
Active chip select to RDY delay time
Tdrdy
0
12
ns
Active ready Low time
Tvrdy
40
ns
Inactive ready to tri-state delay time
Trdyz
3
ns
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production
testing.
2. C
L
= 100pF on D0-D7, all other outputs are loaded with 50pF.
tCYC
tSUR
tHT
tDOD
TCK
TMS
TDI
TDO
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