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参数资料
| 型号： | LXT386LE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收发器|四|优税PCM-30/E-1 |的CMOS | QFP封装| 100引脚|塑料 |
| 文件页数： | 24/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT386LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
24
Datasheet
required for receive operation. When the LOS condition is cleared, the LOS flag is reset and
another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the
data content at the receiver input during the entire LOS detection period for that channel.
2.2.1.1
E1 Mode
In G.775 mode, a loss of signal is detected if the signal is below 200mV typ. for 32 consecutive
pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit
period) with no more than 15 consecutive zeros and the signal level exceeds 250mV typ., the LOS
flag is reset and another transition replaces MCLK with the recovered clock at RCLK.
In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048
consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when
the incoming signal has transitions when the signal level is equal or greater than 250mV for more
than 32 consecutive pulse intervals.
2.2.1.2
T1 Mode
The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for
175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse
density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a
pulse. The incoming signal is considered to have transitions when the signal level is equal or
greater than 250mV.
2.2.1.3
Data Recovery Mode
In data recovery mode, the LOS digital timing is derived from a internal self timed circuit. RPOS/
RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775
recommendation. The LXT384 monitors the incoming signal amplitude. Any signal below 200mV
for more than 30
μ
s (typical) will assert the corresponding LOS pin. The LOS condition is cleared
when the signal amplitude rises above 250mV. The LXT384 requires more than 10 and less than
255 bit periods to declare a LOS condition in accordance to ITU G.775.
2.2.2
Alarm Indication Signal (AIS) Detection
The AIS detection is performed by the receiver independent of any loopback mode. This feature is
available in host mode only with clock recovery. Because there is no clock in data recovery mode,
AIS detection will not work in that mode. AIS requires MCLK to have clock applied, since this
function depends on the clock to count the number of ones in an interval.
2.2.2.1
E1 Mode
Two different detection modes are available depending on the
LACS
register setting:
ETSI ETS300233 Mode
The AIS condition is declared when the received data stream contains less than 3 zeros within
a period of 512 bits.
The AIS condition is cleared when 3 or more zeros within 512 bits are detected.
ITU G.775 Mode
The AIS condition is declared when, within two consecutive 512 bit periods, less than 3 zeros
are detected for each 512 bit period.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LXT388LE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400 | 制造商:LVL1 制造商全称:LVL1 功能描述:All Rate Extended Range Switched 56/DDS Transceiver |
| LXT400JE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Transceiver Circuit For Telecommunications |
| LXT441 | 制造商:LVL1 制造商全称:LVL1 功能描述:Switched 56/DDS Integrated DSU/CSU |
| LXT6155 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:155 Mbps SDH/SONET/ATM Transceiver |
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