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参数资料
| 型号： | LXT388LE |
| 英文描述： | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收发器|双|优税PCM-30/E-1 |的CMOS | QFP封装| 100引脚|塑料 |
| 文件页数： | 23/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT388LE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
23
2.1.1
Reset Operation
Writing to the reset register (RES) initiates a 1 microsecond reset cycle, except in Intel non-
multiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2 microseconds. Please
refer to Host mode section for more information. This operation sets all LXT384 registers to their
default values.
2.2
Receiver
The eight receivers in the LXT384 are identical. The following paragraphs describe the operation
of one.
The twisted-pair input is received via a 1:2 step down transformer. Positive pulses are received at
RTIP, negative pulses at RRING. Recovered data is output at RPOS and RNEG in the bipolar mode
and at RDATA in the unipolar mode. The recovered clock is output at RCLK. RPOS/RNEG
validation relative to RCLK is pin selectable (CLKE).
The receive signal is processed through the peak detector and data slicers. The peak detector
samples the received signal and determines its maximum value. A percentage of the peak value is
provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1
applications (line length inputs LEN2-0 from 011 to 111) the threshold is set to 70% (typical) of the
peak value. This threshold is maintained above the specified level for up to 15 successive zeros
over the range of specified operating conditions. For E1 applications (LEN2-0 = 000), the
threshold is 50% (typical).
The receiver is capable of accurately recovering signals with up to 12 dB of attenuation (from 2.4
V), corresponding to a received signal level of approximately 500 mV. Maximum line length is
1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level,
the peak detectors are held above a minimum level of 0.150 V (typical) to provide immunity from
impulsive noise.
After processing through the data slicers, the received signal goes to the data and timing recovery
section. The data and timing recovery circuits provide an input jitter tolerance better than required
by Pub 62411 and ITU G.823, as shown in Test Specifications,
Figure 33
.
Depending on the options selected, recovered clock and data signals may be routed through the
jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either
bipolar or unipolar data.
2.2.1
Loss of Signal Detector
The loss of signal detector in the LXT384 uses a dedicated analog and digital loss of signal
detection circuit. It is independent of its internal data slicer comparators and complies to the latest
ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be
configured to comply to the ETSI ETS 300 233 specification (
LACS
Register). In hardware mode,
the LXT384 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation.
The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented
each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the
operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is
replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is
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