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参数资料
| 型号： | LXT388LE |
| 英文描述： | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收发器|双|优税PCM-30/E-1 |的CMOS | QFP封装| 100引脚|塑料 |
| 文件页数： | 36/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT388LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
36
Datasheet
delay to allow the reset cycle to completely initialize the device before proceeding. The overall
duration of the Reset cycle from CS low to Reset cycle completion is 3 microseconds when using
Intel non-multiplexed host mode.
An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to
the microprocessor.
The LXT384 has a 5-bit address bus and provides 22 user accessible 8-bit registers for
configuration, alarm monitoring and control of the chip.
2.12.1
Motorola Interface
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode,
the falling edge of DS is used to latch the address information on the address bus. In multiplexed
operation the address on the multiplexed address data bus is latched into the device with the falling
edge of AS. In non-multiplexed mode, AS should be pulled High.
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference
for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/
W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising
edge on DS.
Both cycles require the CS signal to be Low and the Address pins to be actively driven by the
microprocessor. Note: CS and DS can be connected together in Motorola mode. In a write cycle,
the data bus is driven by the microprocessor. In a read cycle, the bus is driven by the LXT384.
2.12.2
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT384 supports non-
multiplexed interfaces with separate address and data pins when MUX is asserted Low, and
multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of
ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS
is used as the WR signal. A read cycle is indicated to the LXT384 when the processor asserts RD
Low while the WR signal is held High. A write operation is indicated to the LXT384 by asserting
WR Low while the RD signal is held High. Both cycles require the CS signal to be Low.
2.13
Interrupt Handling
2.13.1
Interrupt Sources
There are three interrupt sources:
Status change in the LOS (Loss of Signal) status register (04H). The LXT384 analog/digital
loss of signal processor continuously monitors the receiver signal and updates the specific
LOS status bit to indicate presence or absence of a LOS condition.
Status change in the DFM (Driver Failure Monitoring) status register (05H). The LXT384
smart power driver circuit continuously monitors the output drivers signal and updates the
specific DFM status bit to indicate presence or absence of a secondary driver short circuit
condition.
Status change in the AIS (Alarm Indication Signal) status register (13H). The LXT384
receiver monitors the incoming data stream and updates the specific AIS status bit to indicate
presence or absence of a AIS condition.
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相关代理商/技术参数 |
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| LXT400 | 制造商:LVL1 制造商全称:LVL1 功能描述:All Rate Extended Range Switched 56/DDS Transceiver |
| LXT400JE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Transceiver Circuit For Telecommunications |
| LXT441 | 制造商:LVL1 制造商全称:LVL1 功能描述:Switched 56/DDS Integrated DSU/CSU |
| LXT6155 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:155 Mbps SDH/SONET/ATM Transceiver |
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