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参数资料
| 型号： | LXT388LE |
| 英文描述： | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收发器|双|优税PCM-30/E-1 |的CMOS | QFP封装| 100引脚|塑料 |
| 文件页数： | 3/80页 |
| 文件大小： | 1112K |
| 代理商： | LXT388LE |
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Datasheet
3
Octal T1/E1/J1 Line Interface Unit — LXT384
Contents
1.0
Pin Assignments and Signal Descriptions..........................................................................9
2.0
Functional Description......................................................................................................22
2.1
Initialization..........................................................................................................22
2.1.1
Reset Operation .....................................................................................23
2.2
Receiver..............................................................................................................23
2.2.1
Loss of Signal Detector ..........................................................................23
2.2.1.1 E1 Mode....................................................................................24
2.2.1.2 T1 Mode ....................................................................................24
2.2.1.3 Data Recovery Mode.................................................................24
2.2.2
Alarm Indication Signal (AIS) Detection .................................................24
2.2.2.1 E1 Mode....................................................................................24
2.2.2.2 T1 Mode ....................................................................................25
2.2.3
Receive Alarm Indication Signal (RAIS).................................................25
2.2.4
In Service Code Violation Monitoring .....................................................25
2.3
Transmitter..........................................................................................................25
2.3.1
Transmit Pulse Shaping .........................................................................26
2.3.1.1 Hardware Mode.........................................................................26
2.3.1.2 Host Mode.................................................................................26
2.3.1.3 Output Driver Power Supply......................................................27
2.3.1.4 Power Sequencing ....................................................................27
2.4
Driver Failure Monitor..........................................................................................27
2.5
Line Protection ....................................................................................................30
2.6
Jitter Attenuation .................................................................................................30
2.7
Loopbacks...........................................................................................................31
2.7.1
Analog Loopback....................................................................................31
2.7.2
Digital Loopback.....................................................................................32
2.7.3
Remote Loopback ..................................................................................32
2.7.4
Transmit All Ones (TAOS)......................................................................32
2.8
G.772 Performance Monitoring...........................................................................33
2.9
Hitless Protection Switching (HPS).....................................................................34
2.10
Operation Mode Summary..................................................................................34
2.11
Interfacing with 5V Logic.....................................................................................35
2.12
Parallel Host Interface.........................................................................................35
2.12.1 Motorola Interface ..................................................................................36
2.12.2 Intel Interface..........................................................................................36
2.13
Interrupt Handling................................................................................................36
2.13.1 Interrupt Sources....................................................................................36
2.13.2 Interrupt Enable......................................................................................37
2.13.3 Interrupt Clear ........................................................................................37
2.14
Serial Host Mode.................................................................................................37
3.0
Register Descriptions.......................................................................................................38
4.0
JTAG Boundary Scan.......................................................................................................45
4.1
Overview .............................................................................................................45
4.2
Architecture.........................................................................................................45
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