参数资料
型号: M295V100B-T45N6T
厂商: 意法半导体
英文描述: 8-Bit, 0.1 us MDAC, Parallel Input, Fast Control Signalling for DSP, Easy Micro Interface 16-TSSOP -25 to 85
中文描述: 1兆位的128KB x8或64Kb的x16插槽,启动座单电源闪存
文件页数: 10/22页
文件大小: 155K
代理商: M295V100B-T45N6T
M29F100BT, M29F100BB
10/22
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It isalso readduring EraseSus-
pend when anaddress within ablock beingerased
is accessed.
The bits in the Status Register are summarized in
Table 10, Status Register Bits.
Data Polling Bit (DQ7).
The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read modeand BusRead operationsfrom thead-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6).
The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if ithas re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cellwithin a block being
erased. The Toggle Bit will stoptoggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5).
The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase orChip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output onDQ5 when the Status Register is read.
Note that the Programcommand cannot change a
bit setat ’0’ backto ’1’ and attempting to doso may
or may not set DQ5 at ‘1’. In both cases, a succes-
sive Bus Read operation will show the bit is still ‘0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Table 10. Status Register Bits
Note: Unspecified data bits should be ignored.
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
0
Program Error
Any Address
DQ7
Toggle
1
0
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Block Erase before
timeout
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No Toggle
0
Block Erase
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1
No Toggle
0
Erase Suspend
Erasing Block
1
No Toggle
0
Toggle
1
Non-Erasing Block
Data read as normal
1
Erase Error
Good Block Address
0
Toggle
1
1
No Toggle
0
Faulty Block Address
0
Toggle
1
1
Toggle
0
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