参数资料
型号: M295V100B-T45N6T
厂商: 意法半导体
英文描述: 8-Bit, 0.1 us MDAC, Parallel Input, Fast Control Signalling for DSP, Easy Micro Interface 16-TSSOP -25 to 85
中文描述: 1兆位的128KB x8或64Kb的x16插槽,启动座单电源闪存
文件页数: 2/22页
文件大小: 155K
代理商: M295V100B-T45N6T
M29F100BT, M29F100BB
2/22
Figure 2. TSOP Connections
DQ3
DQ10
DQ9
DQ1
DQ2
A6
A5
DQ0
G
VSS
W
A3
A2
A1
RB
NC
DQ6
DQ13
DQ5
A8
NC
A9
NC
A7
A10
DQ14
DQ12
DQ4
DQ15A–1
DQ7
VCC
DQ11
NC
NC
AI02917
M29F100BT
M29F100BB
12
13
1
24
25
36
37
48
DQ8
NC
A4
A12
A11
A13
NC
BYTE
VSS
A15
A14
E
A0
RP
Figure 3. SO Connections
G
DQ0
DQ8
DQ1
DQ9
A3
A2
A1
A0
E
VSS
A13
A14
A15
NC
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
A12
DQ5
DQ12
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
A9
A10
W
A8
RB
NC
A4
NC
RP
A7
A6
A5
AI02918
M29F100BT
M29F100BB
8
9
10
11
12
13
14
15
16
17
2
3
4
5
6
7
32
31
30
29
28
27
26
25
24
23
22
20
21
19
18
44
43
42
41
39
38
37
36
35
34
33
A11
40
1
Table 1. Signal Names
A0-A15
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization Select
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
SUMMARY DESCRIPTION
The M29F100B is a 1 Mbit (128Kbx8 or 64Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single5V supply. On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM. The
M29F100B is fully backward compatible with the
M29F100.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
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