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参数资料
型号： M30102F3TFP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封装： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数： 133/166页
文件大小： 2060K
代理商： M30102F3TFP
Under
development
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
66
(3) Event counter mode
In this mode, the timer counts an external signal fed to CNTR0 pin. (See Table 1.14.5) Figure 1.14.8
shows Timer X mode register in event counter mode.
Item
Specification
Count source
External signals fed to CNTR0 pin (Active edge is selected by software)
Count operation
Down count
When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing When Timer X underflows [Timer X interruption]
Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
CNTR0 pin function
Count source input
TXOUT pin function
Programmable I/O port
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
CNTR0 polarity switching function
The active edge of count source can be selected to be the rising or the falling edge with
software.
Timer X mode register
Symbol
Address
When reset
TXMR
008B16
000000002
Bit name
Function
Bit symbol
W
R
b7 b6 b5 b4 b3 b2 b1 b0
1 0 : Event counter mode
b1 b0
TXMOD2
TXS
TXMOD1
R0EDG
TXMOD0
TXOCNT
CNTR0 polarity
switching bit
Operation mode
select bit 0, 1
0: Counts at rising edge (Interrupt at rising edge)
1: Counts at falling edge(Interrupt at falling edge)
Timer X count
start flag
0 : Stops counting
1 : Starts counting
0 : Set to "0" in event counter mode
0
1 0
0 : Set to "0" in event counter mode
0
(Note 1)
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
Invalid in event counter mode.
When write, set "0". When read, this contents is indeteminate.
TXEDG
TXUND
Invalid in event counter mode.
When write, set "0". When read, this contents is indeteminate.
Figure 1.14.8. Timer X mode register in event counter mode
Table 1.14.5. Specifications of event counter mode
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