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参数资料
型号： M30102F3TFP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封装： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数： 16/166页
文件大小： 2060K
代理商： M30102F3TFP
Under
development
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
109
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Clock asynchronous serial I/O (UART) mode
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag
(TXEPT)
Start
bit
Parity
bit
TxDi
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag
(TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
Transmit interrupt cause select bit = “0”.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Shown in ( ) are bit symbols.
Tc
Transfer clock
D0 D1
D2 D3 D4 D5 D6 D7
ST
P
SP
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
D0 D1 D2 D3
D4 D5 D6
D7
ST
P
SP
D0 D1
ST
Stopped pulsing because transmit enable bit = “0”
Start
bit
Data is set in UARTi transmit buffer register
D0 D1 D2 D3 D4 D5 D6 D7
ST
SP
D8
D0 D1 D2 D3 D4 D5 D6 D7
ST
D8
D0 D1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit
Stop
bit
Data is set in UARTi transmit buffer register.
“0”
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 1.15.12. Typical transmit timings in UART mode
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