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参数资料
型号： M30102F3TFP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封装： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数： 66/166页
文件大小： 2060K
代理商： M30102F3TFP
REVISION HISTORY
M30100/M30102 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
155
B
04/20/01
Figure and Table numbers are revised.
Features are partly revised.
Page numbers of Table of Contents are partly revised.
Figure 1.1.1 to Figure 1.1.3 are partly revised.
Figure 1.1.4 to Figure 1.1.6 are partly revised.
Table 1.1.1 is partly revised.
Figure 1.1.7 is partly revised.
Figure 1.1.8 is partly revised.
Pin description is partly revised.
Explanation of “Memory” is partly revised.
Explanation of “Reset” is partly revised.
Figure 1.5.2 (example reset circuit for voltage check circuit )is added.
Figure 1.5.3 is partly revised.
Figure 1.5.4 is partly revised.
Explanation of “Software Reset” is partly revised.
Processor mode register 0 in Figure 1.5.5 is partly revised. Note 2 is deleted.
Processor mode register 1 is added to Figure 1.5.5.
Figure 1.6.1 and Figure 1.6.2 are partly revised.
Table 1.8.1 is partly revised.
Figure 1.8.1 is partly revised. External RC oscillator is added.
Figure 1.8.4 is partly revised.
Figure 1.8.5 is added.
Explanation of “Stop Mode” is partly revised.
Table 1.8.4 is partly revised.
Figure 1.9.1 is partly revised.
Explanation of “Oscillation Stop Detection Function” is partly revised.
Table 1.10.1 is partly revised.
Figure 1.10.1 is partly revised.
Figure 1.10.2 is partly revised. Note 2 and Note 3 is partly revised. Note 5 is deleted.
Explanation of “Oscillation stop detection interrupt enable bit (CM21) partly revised.
Operation select bit (CM27) is deleted.
Figure 1.11.1 is partly revised.
“UART1 receive interrupt” in (1) Special interrupts is partly revised.
“Timer C interrupt” in (2) Peripheral I/O interrupt is partly revised.
Table 1.12.2 is partly revised.
Figure 1.12.3 is partly revised.
Table 1.12.5 is partly revised.
Figure 1.12.9 is partly revised.
_______
Explanation of “INT interrupt” is partly revised.
External interrupt enable register in Figure 1.12.10 is partly revised.
Explanation of “Key interrupt” is partly revised.
Figure 1.12.13 is partly revised.
Figure 1.12.14 is partly revised.
Explanation of “Watchdog Timer” is partly revised.
Explanation of “Timer 1” is partly revised.
Figure 1.14.2 is partly revised.
Figure 1.14.3 is partly revised. Note 1 and Note 2 are added.
Explanation of “(2) Pulse output mode” is partly revised.
Explanation of “(4) Pulse width measure mode” is partly revised.
All pages
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