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参数资料
型号： M30102F3TFP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封装： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数： 76/166页
文件大小： 2060K
代理商： M30102F3TFP
Under
development
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
14
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer
is reset. The initial values must therefore be set.
(1)
(000416)
Processor mode register 0
(2)
(000516)
Processor mode register 1
(3)
(000616)
System clock control register 0
(4)
(000716)
System clock control register 1
(5)
(6)
(000916)
Address match interrupt
enable register
(7)
(000A16)
(9)
(11)
(12)
(13)
(21)
(20)
(8)
Protect register
(10)
(14)
(15)
(16)
(17)
(18)
(19)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(00A816)
UART1 transmit/receive control
register 0
(00AD16)
UART1 transmit/receive control
register 1
(00B016)
UART transmit/receive control
register 2
(00A016)
UART0 transmit/receive mode
register
(00A416)
UART0 transmit/receive control
register 0
(00A516)
UART0 transmit/receive control
register 1
01001000
00
0
00
0
1
000
0
0 001 00 0
0
00 10
00 0 1 00 0
0
00 10
0016
(00AC16)
UART1 transmit/receive mode
register
(51)
(52)
(49)
(50)
(48)
(53)
(54)
(55)
(56)
(62)
(60)
(61)
(58)
(59)
(57)
(67)
(66)
(68)
(69)
(65)
(00D416)
A-D control register 2
(00D616)
A-D control register 0
(00D716)
A-D control register 1
(63)
(64)
(00E216)
Port P0 direction register
(00E316)
Port P1 direction register
(00E616)
Port P2 direction register
(00E716)
Port P3 direction register
(00EA16)
Port P4 direction register
(00FC16)
Pull-up control register 0
(00FD16)
Pull-up control register 1
(00FE16)
Port P1 drive capacity control
register
Frame base register (FB)
Address registers (A0/A1)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
Data registers (R0/R1/R2/R3)
0 0 00 0? ? ?
0016
000016
0000016
000016
0
(46)
(47)
(45)
UART0 transmit interrupt control
register
UART0 receive interrupt control
register
UART1 transmit interrupt control
register
UART1 receive interrupt control
register
Watchdog timer control register
Key input interrupt control register
Address match interrupt
register 0
A-D conversion interrupt
control register
Timer 1 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
TCIN interrupt control register
Timer C interrupt control register
INT3 interrupt control register
INT1 interrupt control register
Timer Y secondary
Timer Y primary
Timer Y, Z waveform output
control register
Timer Z secondary
Prescaler Y
INT2 interrupt control register
Timer Y, Z mode register
Address match interrupt
register 1
(000F16)
(001416)
(001516)
(001616)
(004D16)
(001016)
(001116)
(001216)
(004E16)
(005116)
(005216)
(005316)
(005416)
(005516)
(005616)
(005716)
(005816)
(005A16)
(005B16)
(005C16)
(005E16)
(008216)
(008316)
(008416)
(008516)
(008616)
(008116)
(005F16)
(008016)
000??? ??
0
FF16
0016
FF16
Timer Z primary
(008716)
FF16
0016
00
0
0016
000
?
000
?
000
?
000
?
000
?
000
?
000
?
000
?
000
?
000
?
000
?
00 0
?
000
?
0 0
000
?
00
0
Oscillation stop detection register
(000C16)
0
00
0
1
0
(001E16)
0
INT0 input filter select register
INT0 interrupt control register
(005D16)
0 0
000
?
0 0
000
?
0
0000 0
FF16
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
Prescaler Z
(71)
(70)
00
0016
(008A16)
Timer Y,Z output control register
(008B16)
Timer X mode register
0
000
0 0
Prescaler X
Timer X
(008C16)
(008D16)
FF16
Timer count source set register
(008E16)
(009616)
External input enable register
(009816)
Key input enable register
(009A16)
Timer C control register 0
0
Clock prescaler reset flag
(008F16) 0
(009B16)
Timer C control register 1
1
(72)
0
0 0
CNTR0 interrupt control register
(005916)
000
?
0
0016
0
(73)
(00DC16)
D-A control register
0
00
Figure 1.5.4. Device's internal status after a reset is cleared
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