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| 型号： | M32180F8TFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP240 |
| 封装： | 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240 |
| 文件页数： | 20/139页 |
| 文件大小： | 3774K |
| 代理商： | M32180F8TFP |
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5
5-5
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.2 ICU Related Registers
5.2.1 Interrupt Vector Register
Interrupt Vector Register (IVECT)
<Address: H’0080 0000>
b0
123456789
10
11
12
13
14
b15
IVECT
????????????????
<After reset: Undefined>
b
Bit Name
Function
R
W
8
IVECT
When an interrupt request is accepted, the 16-low-order
R
N
16 low-order bits of ICU vector table address
bits of the ICU vector table address for the accepted
interrupt request source are stored in this register.
Note: This register must always be accessed in halfwords (2 bytes). (This is a read-only register.)
The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order
bits of the ICU vector table address for the accepted interrupt request source.
Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 0113) must have
set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is
accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are
stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruction
to get the ICU vector table address.
When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware.
(1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK register as
a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source
are masked.)
(2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recognized
interrupt request sources).
(3) The interrupt request (EI) to the CPU core is deasserted.
(4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution).
Notes: Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are disabled
(PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask
Register (IMASK) first before reading the IVECT register.
To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register
(IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. (The
ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler
Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, there-
fore, does not require adding a dummy access.)
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相关代理商/技术参数 |
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| M32180F8VFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series |
| M32180T2-PTC | 功能描述:DEV CONNECTION CNVTR FOR 32180 G RoHS:否 类别:编程器，开发系统 >> 配件 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 标准包装:1 系列:- 附件类型:USB 至 1-Wire? RJ11 适配器 适用于相关产品:1-Wire? 设备 产品目录页面:1429 (CN2011-ZH PDF) |
| M32182F3TFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3UFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3VFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
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