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参数资料
型号： M32180F8TFP
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP240
封装： 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件页数： 27/139页
文件大小： 3774K
代理商： M32180F8TFP
5
5-11
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.3 Interrupt Request Sources in Internal Peripheral I/O
The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O,
A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal
peripheral I/O is described.
Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O
Interrupt Request Sources
Contents
Number of
ICU Type of Input
Input Sources
Source ( Note 1)
TIN3–6 input interrupt request
TIN3–TIN6 inputs
4
Level-recognized
TIN20–29 input interrupt request
TIN20–TIN29 inputs
10
Level-recognized
TIN12–19 input interrupt request
TIN12–TIN19 inputs
8
Level-recognized
TIN0–2 input interrupt request
TIN0–TIN2 inputs
3
Level-recognized
TIN7–11 input interrupt request
TIN7–TIN11 inputs
5
Level-recognized
TMS0,1 output interrupt request
TMS0, TMS1 output
2
Level-recognized
TOP8,9 output interrupt request
TOP8, TOP9 output
2
Level-recognized
TOP10 output interrupt request
TOP10 output
1
Edge-recognized
TIO4–7 output interrupt request
TIO4–TIO7 outputs
4
Level-recognized
TIO8,9 output interrupt request
TIO8, TIO9 outputs
2
Level-recognized
TOP0–5 output interrupt request
TOP0–TOP5 outputs
6
Level-recognized
TOP6,7 output interrupt request
TOP6–TOP7 outputs
2
Level-recognized
TIO0–3 output interrupt request
TIO0–TIO3 outputs
4
Level-recognized
DMA0-4 interrupt request
DMA0–4 transfer completed
5
Level-recognized
SIO1 receive interrupt request
SIO1 reception-completed or receive error interrupt
1
Edge-recognized
SIO1 transmit interrupt request
SIO1 transmission-completed or transmit buffer empty
1
Edge-recognized
interrupt
SIO0 receive interrupt request
SIO0 reception-completed or receive error interrupt
1
Edge-recognized
SIO0 transmit interrupt request
SIO0 transmission-completed or transmit buffer empty
1
Edge-recognized
interrupt
A-D0 conversion interrupt request
A-D0 converter’s scan mode one-shot operation,
1
Edge-recognized
single mode or comparate mode completed
TID0 output interrupt request
TID0 output
1
Edge-recognized
TOU0 output interrupt request
TOU0_0–TOU0_7 outputs
8
Level-recognized
DMA5–9 interrupt request
DMA5–9 transfer completed
5
Level-recognized
SIO2,3 transmit/receive interrupt
SIO2,3 reception-completed or receive error interrupt,
4
Level-recognized
request
transmission-completed or transmit buffer empty interrupt
RTD interrupt request
RTD interrupt generation command
1
Edge-recognized
TID1 output interrupt request
TID1 output
1
Edge-recognized
TOU1,2 output interrupt request
TOU1_0–TOU1_7 outputs, TOU2_0–TOU2_7 outputs
16
Level-recognized
SIO4,5 transmit/receive interrupt
SIO4,5 reception-completed or receive error interrupt,
4
Level-recognized
request
transmission-completed or transmit buffer empty interrupt
A-D1 conversion interrupt request
A-D1 converter’s scan mode one-shot operation,
1
Edge-recognized
single mode or comparate mode completed
TID2 output interrupt request
TID2 output
1
Edge-recognized
TIN30–33 input interrupt request
TIN30–TIN33 inputs
4
Level-recognized
CAN0 transmit/receive & error
CAN0 transmission or reception completed, CAN0 error
35
Level-recognized
interrupt request
passive, CAN0 error bus-off, CAN0 bus error, single shot
CAN1 transmit/receive & error
CAN1 transmission or reception completed, CAN1 error
35
Level-recognized
interrupt request
passive, CAN1 error bus-off, CAN1 bus error, single shot
Note 1: ICU type of input source
Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.
Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For
this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.
5.3 Interrupt Request Sources in Internal Peripheral I/O
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