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参数资料
| 型号： | M32180F8TFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP240 |
| 封装： | 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240 |
| 文件页数： | 25/139页 |
| 文件大小： | 3774K |
| 代理商： | M32180F8TFP |
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5
5-9
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.2 ICU Related Registers
9
1011121314
b15)
(b8
123456
b7
b0
ILEVEL
IREQ
0
111
0
<After reset: H’07>
b
Bit Name
Function
R
W
0–2
No function assigned. Fix to "0"
00
(8–10)
3
IREQ
<When edge recognized>
R
W
(11)
Interrupt request bit
At read
0: Interrupt not requested
1: Interrupt requested
At write
0: Clear interrupt request
1: Generate interrupt request
<When level-recognized>
R
0
At read
0: Interrupt not requested
1: Interrupt requested
4
No function assigned. Fix to "0"
00
(12)
5–7
ILEVEL
000: Interrupt priority level 0
R
W
(13–15)
Interrupt priority level bits
001: Interrupt priority level 1
010: Interrupt priority level 2
011: Interrupt priority level 3
100: Interrupt priority level 4
101: Interrupt priority level 5
110: Interrupt priority level 6
111: Interrupt priority level 7 (interrupt disabled)
(1) IREQ (Interrupt Request) bit (Bit 3 or 11)
When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Re-
quest) bit is set to "1".
This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for
level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re-
quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not
cleared in the case of level-recognized interrupt request).
If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in
software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the
same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority.
Note: External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External
Interrupt (EI) to the CPU core can only be deasserted by the following operation:
(1) Reset
(2) IVECT register read
(3) Write to the IMASK register
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M32180F8VFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series |
| M32180T2-PTC | 功能描述:DEV CONNECTION CNVTR FOR 32180 G RoHS:否 类别:编程器，开发系统 >> 配件 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 标准包装:1 系列:- 附件类型:USB 至 1-Wire? RJ11 适配器 适用于相关产品:1-Wire? 设备 产品目录页面:1429 (CN2011-ZH PDF) |
| M32182F3TFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3UFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3VFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
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