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参数资料
| 型号： | M38039GCHWG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封装： | 6 X 6 MM, 0.65 PITCH, FLGA-64 |
| 文件页数： | 30/103页 |
| 文件大小： | 1412K |
| 代理商： | M38039GCHWG |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 32 of 100
3803 Group (Spec.H QzROM version)
<Notes>
The interrupt request bit may be set to “1” in the following cases.
When setting the external interrupt active edge
Related bits:
INT0 interrupt edge selection bit
(bit 0 of interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of interrupt edge selection register (address 003A16))
INT2 interrupt edge selection bit
(bit 3 of interrupt edge selection register (address 003A16))
INT3 interrupt edge selection bit
(bit 4 of interrupt edge selection register (address 003A16))
INT4 interrupt edge selection bit
(bit 5 of interrupt edge selection register (address 003A16))
CNTR0 activate edge switch bit
(bit 2 of timer XY mode register (address 002316))
CNTR1 activate edge switch bit
(bits 6 of timer XY mode register (address 002316))
CNTR2 activate edge switch bit
(bits 5 of timer Z mode register (address 002A16))
When switching the interrupt sources of an interrupt vector
address where two or more interrupt sources are assigned
Related bits:
INT0, INT4 interrupt switch bit
(bit 6 of interrupt edge selection register (address 003A16))
INT0/Timer Z interrupt source selection bit
(bit 0 of interrupt source selection register (address 003916))
Serial I/O2/Timer Z interrupt source selection bit
(bit 1 of interrupt source selection register (address 003916))
INT4/CNTR2 interrupt source selection bit
(bit 4 of interrupt source selection register (address 003916))
CNTR1/Serial I/O3 receive interrupt source selection bit
(bit 6 of interrupt source selection register (address 003916))
AD conversion/Serial I/O3 transmit interrupt source selection bit
(bit 6 of interrupt source selection register (address 003916))
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one
or more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
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