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参数资料
| 型号： | M38039GCHWG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封装： | 6 X 6 MM, 0.65 PITCH, FLGA-64 |
| 文件页数： | 40/103页 |
| 文件大小： | 1412K |
| 代理商： | M38039GCHWG |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 41 of 100
3803 Group (Spec.H QzROM version)
<Notes regarding all modes>
Timer Z write control
Which write control can be selected by the timer Z write control
bit (bit 3) of the timer Z mode register (address 002A16), writing
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected,
the value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset
release, the operation “writing data to both the latch and the timer
at the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
Timer Z read control
A read-out of timer value is impossible in pulse period
measurement mode and pulse width measurement mode. In the
other modes, a read-out of timer value is possible regardless of
count operating or stopped. However, a read-out of timer latch
value is impossible.
Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2
active edge switch bit and the INT1 active edge selection bit.
Switch of count source
When switching the count source by the timer Z count source
se lec tion bi ts, t h e va lue of t imer count is al tered in
inconsiderable amount owing to generating of thin pulses on the
count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
Usage of CNTR2 pin as normal I/O port P47
To use the CNTR2 pin as normal I/O port P47, set timer Z
operating mode bits (b2, b1, b0) of timer Z mode register
(address 002A16) to “000”.
Fig 28. Block diagram of timer Z
P47/CNTR2
“001”
XIN
Output level latch
Programmable one-shot
generating mode
CNTR2 active edge
switch bit
Programmable one-shot
generating mode
Data bus
To timer Z interrupt
request bit
To INT1 interrupt
request bit
Programmable waveform
generating mode
Pulse output mode
CNTR2 active edge switch bit
Pulse output mode
Timer Z operating
mode bits
Port P47
direction register
Port P47
latch
Pulse period measurement mode
Pulse width measurement mode
Timer Z count stop bit
Count source
selection bit
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
C
lo
c
k
f
o
rtim
e
r
z
CNTR2 active edge
switch bit
D
Q
T
“1”
Timer/Event
counter mode
switch bit
“0”
“1”
“0”
P42/INT1
Programmable one-shot
generating circuit
T
Q
S
Q
“100”
“101”
To CNTR2 interrupt
request bit
“0”
f(XCIN)
Edge detection circuit
“1”
“0”
Timer Z low-order latch
Timer Z low-order
Timer Z high-order latch
Timer Z high-order
XCIN
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